rk29: clock: default codec pll rate set to 445.5MHz, auto set dclk_lcdc rate
author黄涛 <huangtao@rock-chips.com>
Fri, 17 Jun 2011 08:46:03 +0000 (16:46 +0800)
committer黄涛 <huangtao@rock-chips.com>
Fri, 17 Jun 2011 09:01:36 +0000 (17:01 +0800)
commit93c336a89cd45750409b0762eba1ccc459b389bd
treea0b33930413c2daeba748058966c9b113f21cb48
parent86061d367c48dc47cb93c2bdee9910ca7084890b
rk29: clock: default codec pll rate set to 445.5MHz, auto set dclk_lcdc rate
arch/arm/mach-rk29/clock.c
arch/arm/mach-rk29/include/mach/board.h
drivers/video/rk29_fb.c