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(parent: 36c0d0c) | patch
drm/i915/guc: Media domain bit needed when notify GuC rc6 state
authorAlex Dai <yu.dai@intel.com>
Fri, 25 Sep 2015 18:46:56 +0000 (11:46 -0700)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 30 Sep 2015 15:15:12 +0000 (17:15 +0200)
commit93f253187c2f565678bd7e5ca5f64c1043774f1b
tree94f192d9534985030b65c03a96c781efbb5c243btree | snapshot
parent36c0d0cf33ed31fada15caac34d50555b33208bbcommit | diff
drm/i915/guc: Media domain bit needed when notify GuC rc6 state

GuC expects two bits for Render and Media domain separately when
driver sends data via host2guc SAMPLE_FORCEWAKE. Bit 0 is for
Render and bit 1 is for Media domain.

v2: Keep sync with code for WaRsDoubleRc6WrlWithCoarsePowerGating

v1: Add parameters definition to avoid magic value

Signed-off-by: Alex Dai <yu.dai@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_guc_submission.c diff | blob | history
drivers/gpu/drm/i915/intel_guc_fwif.h diff | blob | history
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