arm64: Add workaround for Cavium erratum 27456
authorAndrew Pinski <apinski@cavium.com>
Thu, 25 Feb 2016 01:44:57 +0000 (17:44 -0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 15 Sep 2016 06:27:44 +0000 (08:27 +0200)
commit950464b230e007f5206b4a4ac86aeba70524b2f6
tree6f41ffaee183d861d051dd2808ed5b47215650ea
parente7c3692b809bfbcf03cbb70104dc365658b3bfb6
arm64: Add workaround for Cavium erratum 27456

[ Upstream commit 104a0c02e8b1936c049e18a6d4e4ab040fb61213 ]

On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
instructions may cause the icache to become corrupted if it contains
data for a non-current ASID.

This patch implements the workaround (which invalidates the local
icache when switching the mm) by using code patching.

Signed-off-by: Andrew Pinski <apinski@cavium.com>
Signed-off-by: David Daney <david.daney@cavium.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/arm64/Kconfig
arch/arm64/include/asm/cpufeature.h
arch/arm64/kernel/cpu_errata.c
arch/arm64/mm/proc.S