UPSTREAM: drm/rockchip: Optimization vop mode set

UPSTREAM: drm/rockchip: Optimization vop mode set

Rk3288 vop timing registers is immediately register, when configure
timing on display active time, will cause tearing. use dclk reset is
not a good idea to avoid this tearing. we can avoid tearing by using
standby register.

Vop standby register will take effect at end of current frame, and
go back to work immediately when exit standby.

So we can use standby register to protect this context.

Change-Id: Ib65433900c67f9fbd3957c4b0506d6172474e5c2
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(cherry picked from commit ce3887ed0d996e6353d739e8139b8e5faeb726d5)