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ARM: tegra: Enable PL310 dynamic clock gating
authorTodd Poynor <toddpoynor@google.com>
Wed, 16 Feb 2011 20:25:36 +0000 (12:25 -0800)
committerTodd Poynor <toddpoynor@google.com>
Wed, 16 Feb 2011 21:30:34 +0000 (13:30 -0800)
commit996d8ccfe7ee48dabe8f46358159985e0a410c08
tree7a666a37b0869747ae83beaf72001a714f1118d0tree | snapshot
parente4c3b484a4cdc5e3bfb0332f47adaaff827f62abcommit | diff
ARM: tegra: Enable PL310 dynamic clock gating

The cache controller will stop its clock when idle after several
clock cycles.

Change-Id: Ifc9997d4e7fd4f1e3c6129bac2fd42f8995a069e
Signed-off-by: Todd Poynor <toddpoynor@google.com>
arch/arm/mach-tegra/common.c diff | blob | history
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