UPSTREAM: net: phy: dp83867: Fix initialization of PHYCR register

UPSTREAM: net: phy: dp83867: Fix initialization of PHYCR register

When initializing the PHY control register, the FIFO depth bits are
written without reading the previous register value, i.e. all other
bits are overwritten with zero. This disables automatic MDI-X
configuration, which is enabled by default. Fix initialization by doing
a read/modify/write operation.

Signed-off-by: Stefan Hauser <stefan@shauser.net>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit b291c418172f2cfbe009d81cd9a92f7a2de7c579)
Change-Id: If14021286ff6e8b770f6cfe0f4026e29414e75d8
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>