microblaze: Fix unaligned issue on MMU system with BS=0 DIV=1
authorMichal Simek <monstr@monstr.eu>
Fri, 28 Jan 2011 12:14:58 +0000 (13:14 +0100)
committerMichal Simek <monstr@monstr.eu>
Fri, 28 Jan 2011 13:05:00 +0000 (14:05 +0100)
commit9c749e177ccc0b3ee9589425c7255079e7a726fc
tree24a4f8f56b4f6b545bd4c688d50e6d855a43d731
parent026a2078791b64aede220b1b1a3e4dfe4ab175e7
microblaze: Fix unaligned issue on MMU system with BS=0 DIV=1

Unaligned code use shift for finding register operand.
There is used BSRLI(r8,r8,2) macro which is expand for BS=0, DIV=1
by
ori rD, r0, (1 << imm); \
idivu rD, rD, rA

but if rD is equal rA then ori instruction rewrite value which
should be devide.

The patch remove this macro which use idivu instruction because
idivu takes 32/34 cycles. The highest shifting is 20 which takes
20 cycles.

Signed-off-by: Michal Simek <monstr@monstr.eu>
arch/microblaze/kernel/hw_exception_handler.S