More CellSPU refinement and progress:
authorScott Michel <scottm@aero.org>
Fri, 11 Jan 2008 02:53:15 +0000 (02:53 +0000)
committerScott Michel <scottm@aero.org>
Fri, 11 Jan 2008 02:53:15 +0000 (02:53 +0000)
commit9de5d0dd42463f61c4ee2f9db5f3d08153c0dacf
tree0405fe251d353f90861768223bfb36945e3b40fe
parentc37ab63df71e425951ce7a8c797540a18d0a3e63
More CellSPU refinement and progress:

- Cleaned up custom load/store logic, common code is now shared [see note
  below], cleaned up address modes

- More test cases: various intrinsics, structure element access (load/store
  test), updated target data strings, indirect function calls.

Note: This patch contains a refactoring of the LoadSDNode and StoreSDNode
structures: they now share a common base class, LSBaseSDNode, that
provides an interface to their common functionality. There is some hackery
to access the proper operand depending on the derived class; otherwise,
to do a proper job would require finding and rearranging the SDOperands
sent to StoreSDNode's constructor. The current refactor errs on the
side of being conservatively and backwardly compatible while providing
functionality that reduces redundant code for targets where loads and
stores are custom-lowered.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45851 91177308-0d34-0410-b5e6-96231b3b80d8
32 files changed:
include/llvm/CodeGen/SelectionDAGNodes.h
include/llvm/IntrinsicsCellSPU.td
lib/Target/CellSPU/CellSDKIntrinsics.td
lib/Target/CellSPU/SPUISelDAGToDAG.cpp
lib/Target/CellSPU/SPUISelLowering.cpp
lib/Target/CellSPU/SPUISelLowering.h
lib/Target/CellSPU/SPUInstrInfo.td
lib/Target/CellSPU/SPUNodes.td
lib/Target/CellSPU/SPUOperands.td
test/CodeGen/CellSPU/and_ops.ll
test/CodeGen/CellSPU/call_indirect.ll [new file with mode: 0644]
test/CodeGen/CellSPU/ctpop.ll
test/CodeGen/CellSPU/dp_farith.ll
test/CodeGen/CellSPU/eqv.ll
test/CodeGen/CellSPU/extract_elt.ll
test/CodeGen/CellSPU/fcmp.ll
test/CodeGen/CellSPU/fdiv.ll
test/CodeGen/CellSPU/fneg-fabs.ll
test/CodeGen/CellSPU/immed16.ll
test/CodeGen/CellSPU/immed32.ll
test/CodeGen/CellSPU/immed64.ll
test/CodeGen/CellSPU/int2fp.ll
test/CodeGen/CellSPU/intrinsics_branch.ll [new file with mode: 0644]
test/CodeGen/CellSPU/intrinsics_float.ll [new file with mode: 0644]
test/CodeGen/CellSPU/intrinsics_logical.ll [new file with mode: 0644]
test/CodeGen/CellSPU/nand.ll
test/CodeGen/CellSPU/or_ops.ll
test/CodeGen/CellSPU/rotate_ops.ll
test/CodeGen/CellSPU/select_bits.ll
test/CodeGen/CellSPU/shift_ops.ll
test/CodeGen/CellSPU/sp_farith.ll
test/CodeGen/CellSPU/struct_1.ll [new file with mode: 0644]