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[ARM] Allowing SP/PC for AND/BIC mod_imm_not
authorRenato Golin <renato.golin@linaro.org>
Tue, 8 Dec 2015 18:10:58 +0000 (18:10 +0000)
committerRenato Golin <renato.golin@linaro.org>
Tue, 8 Dec 2015 18:10:58 +0000 (18:10 +0000)
commita0beb06ac92b08c8e62c04b3f2d5279785e12e96
tree1da01b0b1cf8954d4d55f6e3c9b81a2f1a9d5d53tree | snapshot
parent72f75faa283d31acd018a40226470b852e39df0bcommit | diff
[ARM] Allowing SP/PC for AND/BIC mod_imm_not

AND/BIC instructions do accept SP/PC, so the register class should be
more generic (rGPR -> GPR) to cope with that case. Adding more tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255034 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM/ARMInstrInfo.td diff | blob | history
test/MC/ARM/basic-arm-instructions.s diff | blob | history
C/C++ LLVM-based compilers that forbids OOTA behaviors