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[ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for...
authorBradley Smith <bradley.smith@arm.com>
Wed, 9 Apr 2014 14:42:11 +0000 (14:42 +0000)
committerBradley Smith <bradley.smith@arm.com>
Wed, 9 Apr 2014 14:42:11 +0000 (14:42 +0000)
commita493b7786a5057135d726abfa78a7b495bcf524a
tree8cddccc11545f1f037ba5f73534db12a8d7ffb25tree | snapshot
parenta5b549e03c036ce4f6a4959ebc344d9d32744070commit | diff
[ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205865 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp diff | blob | history
test/MC/Disassembler/ARM64/arithmetic.txt diff | blob | history
test/MC/Disassembler/ARM64/basic-a64-undefined.txt diff | blob | history
C/C++ LLVM-based compilers that forbids OOTA behaviors