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(parent: f36ad4a) | patch
R600/SI: Update tablegen defs to avoid restoring spilled sgprs to m0
authorTom Stellard <thomas.stellard@amd.com>
Tue, 12 May 2015 15:00:53 +0000 (15:00 +0000)
committerTom Stellard <thomas.stellard@amd.com>
Tue, 12 May 2015 15:00:53 +0000 (15:00 +0000)
commita52fdfb7c76d2417b1ad2175a844decce5e1b521
tree8fc1a71e780d2ea58d11d90c266cfc0491aed87btree | snapshot
parentf36ad4aa049be564bf83afcbea39db6fa1a2ee27commit | diff
R600/SI: Update tablegen defs to avoid restoring spilled sgprs to m0

We had code to do this in SIRegisterInfo::eliminateFrameIndex(), but
it is easier to just change the definition of SI_SPILL_S32_RESTORE to
only allow numbered sgprs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237143 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/R600/SIInstructions.td diff | blob | history
lib/Target/R600/SIRegisterInfo.cpp diff | blob | history
C/C++ LLVM-based compilers that forbids OOTA behaviors