Don't cache the instruction and register info from the TargetMachine, because
authorBill Wendling <isanbard@gmail.com>
Fri, 7 Jun 2013 21:00:34 +0000 (21:00 +0000)
committerBill Wendling <isanbard@gmail.com>
Fri, 7 Jun 2013 21:00:34 +0000 (21:00 +0000)
commita5e5ba611f787f518fd3f7349343f8c4ae863fc2
tree7de9380d58b8555fcc8a89f014acdfe810fdba77
parent1ce4985e019fcb89c6d827ba6cd11e3c4365121b
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183571 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86FastISel.cpp
lib/Target/X86/X86FixupLEAs.cpp
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86ISelLowering.h
lib/Target/X86/X86InstrInfo.cpp
lib/Target/X86/X86RegisterInfo.cpp
lib/Target/X86/X86RegisterInfo.h