drm/i915: Configure GAM_ECOCHK appropriatly for Gen7
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 4 Apr 2013 12:13:42 +0000 (15:13 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 18 Apr 2013 07:43:19 +0000 (09:43 +0200)
commita6f429a5a2f6ae0e1e8df2493884f9a881486d81
tree467d802032ad600e98201ff1756cfc15e9d446da
parenta65c2fcd00518b7339d72e08e6b2b4261fbcc22a
drm/i915: Configure GAM_ECOCHK appropriatly for Gen7

IVB and HSW use different encodings for the PPGTT cacheability bits in
the GAM_ECOCHK register.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_gem_gtt.c
drivers/gpu/drm/i915/i915_reg.h