[ARM] tegra: Set bit 22 in the PL310 AuxCtrl

[ARM] tegra: Set bit 22 in the PL310 AuxCtrl

Duplicate Catalin Marinas' <catalin.marinas@arm.com> ARM change
6395/1 for VExpress to tegra

Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

Change-Id: I37232041c035f5153a7ad73257c6333634a5f4b8
Signed-off-by: Gary King <gking@nvidia.com>