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MIPS: OCTEON: More OCTEONIII support
authorChandrakala Chavva <cchavva@caviumnetworks.com>
Thu, 15 Jan 2015 13:11:17 +0000 (16:11 +0300)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 20 Feb 2015 14:32:46 +0000 (15:32 +0100)
commitac6d9b3a03930820bec0ebd3a28f9dae32d27342
tree69bd6e7b723955f113e977f4f392da9c7de0f469tree | snapshot
parent920cda3870557a50105f0c5eb783059b3aced86ecommit | diff
MIPS: OCTEON: More OCTEONIII support

Read clock rate from the correct CSR. Don't clear COP0_DCACHE for OCTEONIII.

Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8945/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/cavium-octeon/csrc-octeon.c diff | blob | history
arch/mips/cavium-octeon/setup.c diff | blob | history
arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h diff | blob | history
arch/mips/include/asm/octeon/cvmx-rst-defs.h [new file with mode: 0644] blob
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