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(parent: 7ab2009) | patch
[AArch64] Improve ISel using across lane addition reduction.
authorChad Rosier <mcrosier@codeaurora.org>
Thu, 3 Sep 2015 18:13:57 +0000 (18:13 +0000)
committerChad Rosier <mcrosier@codeaurora.org>
Thu, 3 Sep 2015 18:13:57 +0000 (18:13 +0000)
commitad69a64d4aac849d14e51af0bb547a542d4b50bf
treeeb642a182d01cdadc5b75d265d9578d167b3ca45tree | snapshot
parent7ab20090242a84ebba3afa25973fda03be5f2a7ecommit | diff
[AArch64] Improve ISel using across lane addition reduction.

In vectorized add reduction code, the final "reduce" step is sub-optimal.
This change wll combine :

ext  v1.16b, v0.16b, v0.16b, #8
add  v0.4s, v1.4s, v0.4s
dup  v1.4s, v0.s[1]
add  v0.4s, v1.4s, v0.4s

into

addv s0, v0.4s

PR21371
http://reviews.llvm.org/D12325
Patch by Jun Bum Lim <junbuml@codeaurora.org>!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246790 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AArch64/AArch64ISelLowering.cpp diff | blob | history
test/CodeGen/AArch64/aarch64-addv.ll [new file with mode: 0644] blob
C/C++ LLVM-based compilers that forbids OOTA behaviors