omap4: l2x0: Set share override bit
authorSantosh Shilimkar <santosh.shilimkar@ti.com>
Fri, 19 Nov 2010 17:31:05 +0000 (23:01 +0530)
committerTony Lindgren <tony@atomide.com>
Sat, 18 Dec 2010 17:32:55 +0000 (09:32 -0800)
commitb0f20ff9d7e347c284ea7718597c978a2969ad7b
tree376cd6cc0cdb6ad0714b3ea76974179e7ac6e5e8
parent11e0264046e00544eb044fafc27125babd105e41
omap4: l2x0: Set share override bit

Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/mach-omap2/omap4-common.c