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(parent: 5be17c4) | patch
[mips] Correct 128-bit shifts on 64-bit targets.
authorDaniel Sanders <daniel.sanders@imgtec.com>
Wed, 29 Apr 2015 12:28:58 +0000 (12:28 +0000)
committerDaniel Sanders <daniel.sanders@imgtec.com>
Wed, 29 Apr 2015 12:28:58 +0000 (12:28 +0000)
commitb6d2c5a95258adebb2296bd4edd118bbf1168fad
tree61ff6e9b7727d82ad2f463df37a598140708b989tree | snapshot
parent5be17c48fb868e5b687eaeb20aeaf094592dd97fcommit | diff
[mips] Correct 128-bit shifts on 64-bit targets.

Summary:
The existing code was correct for 32-bit GPR's but not 64-bit GPR's. It now
accounts for both cases.

Reviewers: vkalintiris

Reviewed By: vkalintiris

Subscribers: llvm-commits, mohit.bhakkad, sagar

Differential Revision: http://reviews.llvm.org/D9337

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236099 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/Mips/MipsISelLowering.cpp diff | blob | history
test/CodeGen/Mips/llvm-ir/ashr.ll diff | blob | history
test/CodeGen/Mips/llvm-ir/lshr.ll diff | blob | history
test/CodeGen/Mips/llvm-ir/shl.ll diff | blob | history
C/C++ LLVM-based compilers that forbids OOTA behaviors