Machine Model: Add MicroOpBufferSize and resource BufferSize.
authorAndrew Trick <atrick@apple.com>
Sat, 15 Jun 2013 04:49:57 +0000 (04:49 +0000)
committerAndrew Trick <atrick@apple.com>
Sat, 15 Jun 2013 04:49:57 +0000 (04:49 +0000)
commitb86a0cdb674549d8493043331cecd9cbf53b80da
tree8690d4a95ff7cf02b6f840632086b62aa1ed17fc
parentbacb24975d7a8a6ccff0e16057a581b3831c4c7d
Machine Model: Add MicroOpBufferSize and resource BufferSize.

Replace the ill-defined MinLatency and ILPWindow properties with
with straightforward buffer sizes:
MCSchedMode::MicroOpBufferSize
MCProcResourceDesc::BufferSize

These can be used to more precisely model instruction execution if desired.

Disabled some misched tests temporarily. They'll be reenabled in a few commits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184032 91177308-0d34-0410-b5e6-96231b3b80d8
23 files changed:
include/llvm/CodeGen/ScheduleDAG.h
include/llvm/CodeGen/ScheduleDAGInstrs.h
include/llvm/CodeGen/TargetSchedule.h
include/llvm/MC/MCInstrItineraries.h
include/llvm/MC/MCSchedule.h
include/llvm/Target/TargetInstrInfo.h
include/llvm/Target/TargetSchedule.td
lib/CodeGen/MachineScheduler.cpp
lib/CodeGen/MachineTraceMetrics.cpp
lib/CodeGen/ScheduleDAGInstrs.cpp
lib/CodeGen/TargetInstrInfo.cpp
lib/CodeGen/TargetSchedule.cpp
lib/Target/ARM/ARMBaseInstrInfo.cpp
lib/Target/ARM/ARMScheduleA9.td
lib/Target/Hexagon/HexagonMachineScheduler.cpp
lib/Target/X86/X86SchedHaswell.td
lib/Target/X86/X86SchedSandyBridge.td
lib/Target/X86/X86Schedule.td
lib/Target/X86/X86ScheduleAtom.td
test/CodeGen/X86/misched-balance.ll
test/CodeGen/X86/misched-matmul.ll
test/CodeGen/X86/misched-matrix.ll
utils/TableGen/SubtargetEmitter.cpp