KVM: nVMX: Make nested control MSRs per-cpu
authorWincy Van <fanwenyi0529@gmail.com>
Tue, 3 Feb 2015 15:56:30 +0000 (23:56 +0800)
committerPaolo Bonzini <pbonzini@redhat.com>
Tue, 3 Feb 2015 16:06:51 +0000 (17:06 +0100)
commitb9c237bb1db61f107b5d7cee5008e4a6b96ff800
tree406fc00264bc06cfc32c34dd5b093c6bd0411f82
parentf2b93280edee5c7e95eecba48707a4e4a19b17c8
KVM: nVMX: Make nested control MSRs per-cpu

To enable nested apicv support, we need per-cpu vmx
control MSRs:
  1. If in-kernel irqchip is enabled, we can enable nested
     posted interrupt, we should set posted intr bit in
     the nested_vmx_pinbased_ctls_high.
  2. If in-kernel irqchip is disabled, we can not enable
     nested posted interrupt, the posted intr bit
     in the nested_vmx_pinbased_ctls_high will be cleared.

Since there would be different settings about in-kernel
irqchip between VMs, different nested control MSRs
are needed.

Signed-off-by: Wincy Van <fanwenyi0529@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
arch/x86/kvm/vmx.c