clk: rockchip: rk3399: add pll up and down when change pll freq
authorElaine Zhang <zhangqing@rock-chips.com>
Mon, 25 Jul 2016 02:31:58 +0000 (10:31 +0800)
committerGerrit Code Review <gerrit@rock-chips.com>
Tue, 26 Jul 2016 01:54:26 +0000 (09:54 +0800)
commitc98c6d78734dc43dad4ebdca16f5d5470dff7c22
tree8e35a63494b8163eaaa149d7b79c1991450e1074
parent894fca8f3cddc1364c4cfa25eadfa27ac1d1a9d8
clk: rockchip: rk3399: add pll up and down when change pll freq

set pll sequence:
->set pll to slow mode or other plls
->set pll down
->set pll params
->set pll up
->wait pll lock status
->set pll to normal mode

To slove the system error:
rockchip_rk3399_wait_pll_lock: timeout waiting for pll to lock
rockchip_rk3399_pll_set_params: pll update unsucessful,
trying to restore old params

Change-Id: I62aecd9f292de5a3c7bcd8a87231785bf115159d
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
drivers/clk/rockchip/clk-pll.c