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pinctrl: rockchip: fix rk3288 gpio0 configuration
authorChris Zhong <zyw@rock-chips.com>
Wed, 2 Sep 2015 07:59:38 +0000 (15:59 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Mon, 14 Sep 2015 12:01:03 +0000 (20:01 +0800)
commitcbf1d23ba59bb9df494335e50092913412da9dc0
tree40ddd75d1423d0a93785aa61d5b63de7621160d7tree | snapshot
parent92e7da2818b9dd75d125d017898e30ec4f9c9ee0commit | diff
pinctrl: rockchip: fix rk3288 gpio0 configuration

On rk3288, for gpio bank 0, the registers which configure pull-up,
iomux, and drive strength don't implement the enable bits in the upper
half of the register, unlike the other gpio configuration registers,
and so the kernel must perform a read-modify-write of the register to
update a particular gpio in that bank.

Change-Id: I4a6953839307e3a75b2ac554aac3dc865583617d
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
drivers/pinctrl/pinctrl-rockchip.c diff | blob | history
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