author | Matt Arsenault <Matthew.Arsenault@amd.com> | |
Thu, 24 Sep 2015 19:52:27 +0000 (19:52 +0000) | ||
committer | Matt Arsenault <Matthew.Arsenault@amd.com> | |
Thu, 24 Sep 2015 19:52:27 +0000 (19:52 +0000) | ||
commit | d0edb1f758970506b44883154088bc83f8d1da35 | |
tree | 63a05fc998d7166fbd549d322cd39a9cdac04e67 | tree | snapshot |
parent | 1348e9d04d0b29a511efedaa0016a17c86c7bcf7 | commit | diff |
include/llvm/IR/IntrinsicsAMDGPU.td | diff | blob | history | |
lib/Target/AMDGPU/CIInstructions.td | diff | blob | history | |
lib/Target/AMDGPU/SIInsertWaits.cpp | diff | blob | history | |
lib/Target/AMDGPU/SIInstrInfo.td | diff | blob | history | |
lib/Target/AMDGPU/SIInstructions.td | diff | blob | history | |
lib/Target/AMDGPU/VIInstructions.td | diff | blob | history | |
test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll | [new file with mode: 0644] | blob |
test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll | [new file with mode: 0644] | blob |
test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll | [new file with mode: 0644] | blob |
test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll | [new file with mode: 0644] | blob |
test/MC/AMDGPU/smem.s | [new file with mode: 0644] | blob |
test/MC/AMDGPU/smrd.s | diff | blob | history |