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rk3368: clk: fix rk3368 apll set_rate
authordkl <dkl@rock-chips.com>
Sat, 13 Dec 2014 04:00:23 +0000 (12:00 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Sat, 13 Dec 2014 05:42:37 +0000 (13:42 +0800)
commitd18042afb549749b8692f2cfc0e7f49d6c4a98aa
treebfb33e83b6b4014511c81adf16edfb37ed4b3e69tree | snapshot
parentf4c8e2cdacc0ca8574aa632c7436114bc416b6c4commit | diff
rk3368: clk: fix rk3368 apll set_rate

In rk3368, apll enter slow mode before changing settings
and return to normal mode after changing settings.

Signed-off-by: dkl <dkl@rock-chips.com>
drivers/clk/rockchip/clk-pll.c diff | blob | history
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