AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiat...
authorIgor Breger <igor.breger@intel.com>
Wed, 23 Dec 2015 08:06:50 +0000 (08:06 +0000)
committerIgor Breger <igor.breger@intel.com>
Wed, 23 Dec 2015 08:06:50 +0000 (08:06 +0000)
commitd34ae248c07aac9e00b6d505c4d56e95de66c244
tree439bba64b977d72e57d190c02a46c03bac9f989a
parent0f16f3c826def2829befdbff764ef3d8ada3032c
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts.

Differential Revision: http://reviews.llvm.org/D15713

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256324 91177308-0d34-0410-b5e6-96231b3b80d8
13 files changed:
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86InstrAVX512.td
lib/Target/X86/X86InstrSSE.td
test/CodeGen/X86/avx-isa-check.ll
test/CodeGen/X86/vector-shift-ashr-128.ll
test/CodeGen/X86/vector-shift-ashr-256.ll
test/CodeGen/X86/vector-shift-ashr-512.ll
test/CodeGen/X86/vector-shift-lshr-128.ll
test/CodeGen/X86/vector-shift-lshr-256.ll
test/CodeGen/X86/vector-shift-lshr-512.ll
test/CodeGen/X86/vector-shift-shl-128.ll
test/CodeGen/X86/vector-shift-shl-256.ll
test/CodeGen/X86/vector-shift-shl-512.ll