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(parent: fda5f73) | patch
mmc: dw_mmc: correct the calculation for CLKDIV
authorSeungwon Jeon <tgih.jun@samsung.com>
Tue, 22 May 2012 04:01:21 +0000 (13:01 +0900)
committerChris Ball <cjb@laptop.org>
Wed, 6 Jun 2012 13:38:51 +0000 (09:38 -0400)
commite419990b5e811027b1552cbc5b76a6cc180f7f48
tree12791ff201b9e56f74caaa86c22ce0964a8effcctree | snapshot
parentfda5f736864c46324dbc50246ef1ca0e84ebf4aecommit | diff
mmc: dw_mmc: correct the calculation for CLKDIV

In case of "host->bus_hz < slot->clock", divider value is
miscalculated. And clock divider register value is multiple of 2. If
calculated divider value is odd number, result can be over-clocking.

Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
Acked-by: Will Newton <will.newton@gmail.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
drivers/mmc/host/dw_mmc.c diff | blob | history
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