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(parent: a5e5ba6) | patch
Don't cache the instruction and register info from the TargetMachine, because
authorBill Wendling <isanbard@gmail.com>
Fri, 7 Jun 2013 21:04:35 +0000 (21:04 +0000)
committerBill Wendling <isanbard@gmail.com>
Fri, 7 Jun 2013 21:04:35 +0000 (21:04 +0000)
commite488b4ecdc6bf9a4a2d53f9311827f92c9044db1
tree9911bf5f6c41d1a9d6de05c906072a9769e848b2tree | snapshot
parenta5e5ba611f787f518fd3f7349343f8c4ae863fc2commit | diff
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183572 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/XCore/XCoreInstrInfo.cpp diff | blob | history
lib/Target/XCore/XCoreRegisterInfo.cpp diff | blob | history
lib/Target/XCore/XCoreRegisterInfo.h diff | blob | history
C/C++ LLVM-based compilers that forbids OOTA behaviors