MIPS: BCM63XX: fix BCM6345 clocks bits
authorFlorian Fainelli <florian@openwrt.org>
Mon, 12 Nov 2012 08:48:45 +0000 (08:48 +0000)
committerJohn Crispin <blogic@openwrt.org>
Tue, 20 Nov 2012 07:30:50 +0000 (08:30 +0100)
commite59b008e14c63572d4c643592e84bbd1b4088f39
treeb69661b59829de3b4e69ad43858000cab5ef9fab
parent0224cde212df4abf251f89c3724a800b1949a774
MIPS: BCM63XX: fix BCM6345 clocks bits

BCM6345 has an intermediate 16-bits wide test control register between the
peripheral identifier register, and its clock control register is only 16-bits
wide contrary to other platforms where it is 32-bits wide. By shifting all
clocks bits by 16-bits to the left we ensure they get written to the proper
clock control register, without adding specific BCM6345 handling in the clock
code.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4555/
Signed-off-by: John Crispin <blogic@openwrt.org>
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h