video: tegra: host1x driver

video: tegra: host1x driver

the graphics and display hardware on tegra SoCs is accessed
through a command DMA front-end called host1x

host driver clients place commands into memory objects called
streams, and submit a stream on one of 8 channels: the assignment
of streams-to-channels depends on the hardware module(s) programmed
by the stream: for example, all streams which program the 3D
hardware are submitted on channel 1.

the host1x hardware includes two synchronization primitives to
allow command streams to synchronize access to memory or to
hardware engines shared across channels (e.g. the 2D blitter):
sync points and module mutexes. both primitives can also be
used to synchronize with the CPU.

the host1x driver performs power management for all modules
behind the host block: once a module is idle (i.e., the
last stream which accesses it has completed, indicated by
a syncpoint) and has remained idle for an extended period
of time, the module's clock (and power gate island, if the
module is uniquely power-gated) is disabled, and will be
automatically re-enabled when a new stream is submitted for
that module.

includes channel debugging support originally implemented
by Erik Gilling <konkers@google.com>

Original Author: Antti Hatala <ahatala@nvidia.com>
Signed-off-by: Gary King <gking@nvidia.com>
Change-Id: Idf0ecc8e7710f3839903a9fbfbe5650990a96b2c