rockchip: clk: rk3399: make the cpll as parent just for vop
authorElaine Zhang <zhangqing@rock-chips.com>
Mon, 12 Sep 2016 01:57:04 +0000 (09:57 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Thu, 5 Jan 2017 00:58:15 +0000 (08:58 +0800)
commite865e4f1cbe0fbb02e0cccbd3e4829b5a706fc39
tree0f8b0341207e937f7ee2ad6be92158c887f3f4ae
parent945d99a5ecf41a5797ee1c22908d1d710f484f0b
rockchip: clk: rk3399: make the cpll as parent just for vop

others clk change it's parent from cpll to dummy_cpll.
the vop's parent just vpll and cpll,
make sure each vop have it's own pll as parent.

Change-Id: Ia61e10918e14a69c053455018ddf0183ff15ea19
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
drivers/clk/rockchip/clk-rk3399.c
include/dt-bindings/clock/rk3399-cru.h