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R600: Fix LowerSDIV24
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 24 Jul 2014 06:59:20 +0000 (06:59 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 24 Jul 2014 06:59:20 +0000 (06:59 +0000)
commitf303d037f248109e01eda9fd95d4e92d2efb8116
tree43b9cb7e977c24349193e0b425406eb77888045etree | snapshot
parent897105001238e442118ed77561f5e55935dd0d0ecommit | diff
R600: Fix LowerSDIV24

Use ComputeNumSignBits instead of checking for i8 / i16 which only
worked when AMDIL was lying about having legal i8 / i16.

If an integer is known to fit in 24-bits, we can
do division faster with float ops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213843 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/R600/AMDGPUISelLowering.cpp diff | blob | history
test/CodeGen/R600/sdiv24.ll [new file with mode: 0644] blob
C/C++ LLVM-based compilers that forbids OOTA behaviors