clk: rockchip: rk3288: i2s_frac adds flag to set parent's rate
authorJianqun <jay.xu@rock-chips.com>
Tue, 30 Sep 2014 03:12:04 +0000 (11:12 +0800)
committerHeiko Stuebner <heiko@sntech.de>
Wed, 1 Oct 2014 08:55:13 +0000 (10:55 +0200)
commitfc69ed70c16a31d6a77ec47a30a9fe941f763f1e
treed29c2d76beb5b092267c8e4d69c2045b0d99abf6
parent0e5bdb3f9fa5c2bd4452c258de78122ef15f62d6
clk: rockchip: rk3288: i2s_frac adds flag to set parent's rate

The relation of i2s nodes as follows:
          i2s_src               0           0            594000000  0
             i2s_frac           0           0            11289600   0
                i2s_pre         0           0            11289600   0
                   sclk_i2s0    0           0            11289600   0
                   i2s0_clkout  0           0            11289600   0
                      hclk_i2s0 1           1            99000000   0

sclk_i2s0 is the master clock, when to set rate of sclk_i2s0, should
allow to set its parent's rate, by add flag CLK_SET_RATE_PARENT for
"i2s_frac", "i2s_pre", "i2s0_clkout" and "sclk_i2s0".

Tested on rk3288 board using max98090, with command "aplay <music.wav>"

Change-Id: I12faad082566532b65a7de8c0a6845e1c17870e6
Signed-off-by: Jianqun <jay.xu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rk3288.c