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rk3368: clk: fix rk3368 apllb/aplll set_rate
authordkl <dkl@rock-chips.com>
Sat, 13 Dec 2014 12:55:04 +0000 (20:55 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Sat, 13 Dec 2014 13:10:11 +0000 (21:10 +0800)
commitfd28f459b1ce4350bbd7bae1c8755a0a8b3ddfe0
tree4e1df442ff6ce48ced9898b62d09773508646190tree | snapshot
parentfd62e6c91e90e952a2f303dbb7738939e464c863commit | diff
rk3368: clk: fix rk3368 apllb/aplll set_rate

After rk3368 apllb/aplll change settings, set the divider of core back to 1.

Signed-off-by: dkl <dkl@rock-chips.com>
drivers/clk/rockchip/clk-pll.c diff | blob | history
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