PCI: support sizing P2P bridge I/O windows with 1K granularity
authorYinghai Lu <yinghai@kernel.org>
Tue, 10 Jul 2012 01:55:29 +0000 (19:55 -0600)
committerBjorn Helgaas <bhelgaas@google.com>
Tue, 10 Jul 2012 01:55:29 +0000 (19:55 -0600)
commitfd591341102ba5eb9e517d3889e7566fa45e021e
treee4e658bac28fe3626c9507a459d648d14a007b5e
parent2b28ae1912e5ce5bb0527e352ae6ff04e76183d1
PCI: support sizing P2P bridge I/O windows with 1K granularity

Some bridges support I/O windows with 1K alignment, not just the 4K
alignment defined by the PCI spec.  For example, see the IOBL_ADR register
and the EN1K bit in the CNF register in the Intel 82870P2 (P64H2).

This patch adds support for sizing the window in 1K increments based
on the requirements of downstream devices.

[bhelgaas: changelog, comment]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
drivers/pci/setup-bus.c