(outs GPR32:$Rd)>;
-let Rd = 0b11111, isCompare = 1 in {
+let SchedRW = [WriteCMP, ReadCMP, ReadCMP], Rd = 0b11111, isCompare = 1 in {
defm CMNx : addsub_exts<0b1, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>,
(outs), extends_to_i64>,
addsub_xxtx< 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>, (outs)>;
[(set NZCV,
(A64cmp Ty:$Rn, cmp_imm_operand:$Imm12))],
NoItinerary>,
- Sched<[WriteALU, ReadALU]> {
+ Sched<[WriteCMP, ReadCMP]> {
let Rd = 0b11111;
let Defs = [NZCV];
let isCompare = 1;
A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
(ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
"bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
- Sched<[WriteALU, ReadALU]> {
+ Sched<[WriteALU, ReadALU, ReadALU]> {
let DecoderMethod = "DecodeBitfieldInstruction";
let Constraints = "$src = $Rd";
}
A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
(ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
"bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
- Sched<[WriteALU, ReadALU]> {
+ Sched<[WriteALU, ReadALU, ReadALU]> {
let DecoderMethod = "DecodeBitfieldInstruction";
let Constraints = "$src = $Rd";
}
def BFXILwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
(ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
"bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
- Sched<[WriteALU, ReadALU]> {
+ Sched<[WriteALU, ReadALU, ReadALU]> {
// As above, no disassembler allowed.
let isAsmParserOnly = 1;
let Constraints = "$src = $Rd";
def BFXILxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
(ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
"bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
- Sched<[WriteALU, ReadALU]> {
+ Sched<[WriteALU, ReadALU, ReadALU]> {
// As above, no disassembler allowed.
let isAsmParserOnly = 1;
let Constraints = "$src = $Rd";
def BFIwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
(ins GPR32:$src, GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
"bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
- Sched<[WriteALU, ReadALU]> {
+ Sched<[WriteALU, ReadALU, ReadALU]> {
// As above, no disassembler allowed.
let isAsmParserOnly = 1;
let Constraints = "$src = $Rd";
def BFIxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
(ins GPR64:$src, GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
"bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
- Sched<[WriteALU, ReadALU]> {
+ Sched<[WriteALU, ReadALU, ReadALU]> {
// As above, no disassembler allowed.
let isAsmParserOnly = 1;
let Constraints = "$src = $Rd";
(outs),
(ins GPR:$Rn, GPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),
!strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),
- [], NoItinerary> {
+ [], NoItinerary>,
+ Sched<[WriteCMP, ReadCMP, ReadCMP]> {
let Defs = [NZCV];
}
!strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
[(set i32:$Rd, (select i32:$Rn, i32:$Rm))],
NoItinerary>,
- Sched<[WriteCMP, ReadCMP]>;
+ Sched<[WriteCMP, ReadCMP, ReadCMP]>;
def xxxc : A64I_condsel<0b1, op, 0b0, op2,
!strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
[(set i64:$Rd, (select i64:$Rn, i64:$Rm))],
NoItinerary>,
- Sched<[WriteCMP, ReadCMP]>;
+ Sched<[WriteCMP, ReadCMP, ReadCMP]>;
}
}
def X_wwx : A64I_dp_2src<0b1, {0, 1, 0, c, 1, 1}, 0b0,
!strconcat(asmop, "x\t$Rd, $Rn, $Rm"),
(outs GPR32:$Rd), (ins GPR32:$Rn, GPR64:$Rm), [],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteALU, ReadALU, ReadALU]>;
}
multiclass dp_2src_zext <bits<6> opcode, string asmop, SDPatternOperator op> {
(outs), (ins prefetch_op:$Rt, ldrlit_label:$Imm19),
"prfm\t$Rt, $Imm19",
[], NoItinerary>,
- Sched<[WriteLd]>;
+ Sched<[WriteLd, ReadLd]>;
}
//===----------------------------------------------------------------------===//
multiclass A64I_SRex<string asmstr, bits<3> opcode, string prefix> {
def _byte: A64I_SRexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
(outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteSt, ReadSt, ReadSt]>;
def _hword: A64I_SRexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
(outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
- [],NoItinerary>;
+ [],NoItinerary>,
+ Sched<[WriteSt, ReadSt, ReadSt]>;
def _word: A64I_SRexs_impl<0b10, opcode, asmstr,
(outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteSt, ReadSt, ReadSt]>;
def _dword: A64I_SRexs_impl<0b11, opcode, asmstr,
(outs GPR32:$Rs), (ins GPR64:$Rt, GPR64xsp0:$Rn),
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteSt, ReadSt, ReadSt]>;
}
defm STXR : A64I_SRex<"stxr", 0b000, "STXR">;
def _byte: A64I_SLexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
(outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
[(atomic_store_release_8 i64:$Rn, i32:$Rt)],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteSt, ReadSt, ReadSt]>;
def _hword: A64I_SLexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
(outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
[(atomic_store_release_16 i64:$Rn, i32:$Rt)],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteSt, ReadSt, ReadSt]>;
def _word: A64I_SLexs_impl<0b10, opcode, asmstr,
(outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
[(atomic_store_release_32 i64:$Rn, i32:$Rt)],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteSt, ReadSt, ReadSt]>;
def _dword: A64I_SLexs_impl<0b11, opcode, asmstr,
(outs), (ins GPR64:$Rt, GPR64xsp0:$Rn),
[(atomic_store_release_64 i64:$Rn, i64:$Rt)],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteSt, ReadSt, ReadSt]>;
}
defm STLR : A64I_SLex<"stlr", 0b101, "STLR">;
def _word: A64I_SPexs_impl<0b10, opcode, asmstr, (outs),
(ins GPR32:$Rs, GPR32:$Rt, GPR32:$Rt2,
GPR64xsp0:$Rn),
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteSt, ReadSt, ReadSt, ReadSt]>;
def _dword: A64I_SPexs_impl<0b11, opcode, asmstr, (outs),
(ins GPR32:$Rs, GPR64:$Rt, GPR64:$Rt2,
GPR64xsp0:$Rn),
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteSt, ReadSt, ReadSt, ReadSt]>;
}
defm STXP : A64I_SPex<"stxp", 0b010>;
(outs GPR32:$Rt, GPR32:$Rt2),
(ins GPR64xsp0:$Rn),
[], NoItinerary>,
- Sched<[WriteLd]>;
+ Sched<[WriteLd, WriteLd, ReadLd]>;
def _dword: A64I_LPexs_impl<0b11, opcode, asmstr,
(outs GPR64:$Rt, GPR64:$Rt2),
(ins GPR64xsp0:$Rn),
[], NoItinerary>,
- Sched<[WriteLd]>;
+ Sched<[WriteLd, WriteLd, ReadLd]>;
}
defm LDXP : A64I_LPex<"ldxp", 0b010>;
def _STR : A64I_LSunsigimm<size, v, {high_opc, 0b0},
(outs), (ins GPR:$Rt, GPR64xsp:$Rn, params.uimm12:$UImm12),
"str" # asmsuffix # "\t$Rt, [$Rn, $UImm12]",
- [], NoItinerary> {
+ [], NoItinerary>,
+ Sched<[WriteSt, ReadSt, ReadSt]> {
let mayStore = 1;
}
def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn]",
(outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR32:$Rm,
params.regextWm:$Ext),
"str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteSt, ReadSt, ReadSt, ReadSt]>;
def _Xm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b1,
(outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR64:$Rm,
params.regextXm:$Ext),
"str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteSt, ReadSt, ReadSt, ReadSt]>;
}
def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn, $Rm]",
(!cast<Instruction>(prefix # "_Xm_RegOffset_STR") GPR:$Rt, GPR64xsp:$Rn,
def _STUR : A64I_LSunalimm<size, v, {high_opc, 0b0},
(outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
"stur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
- [], NoItinerary> {
+ [], NoItinerary>,
+ Sched<[WriteSt, ReadSt, ReadSt]> {
let mayStore = 1;
}
def : InstAlias<"stur" # asmsuffix # " $Rt, [$Rn]",
(outs GPR64xsp:$Rn_wb),
(ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
"str" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
- [], NoItinerary> {
+ [], NoItinerary>,
+ Sched<[WriteSt, ReadSt, ReadSt]> {
let Constraints = "$Rn = $Rn_wb";
let mayStore = 1;
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldr" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
[], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ Sched<[WriteLd, WriteLd, ReadLd]> {
let mayLoad = 1;
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeSingleIndexedInstruction";
(outs GPR64xsp:$Rn_wb),
(ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
"str" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
- [], NoItinerary> {
+ [], NoItinerary>,
+ Sched<[WriteSt, ReadSt, ReadSt]> {
let Constraints = "$Rn = $Rn_wb";
let mayStore = 1;
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
[], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ Sched<[WriteLd, WriteLd, ReadLd]> {
let mayLoad = 1;
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeSingleIndexedInstruction";
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
[], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ Sched<[WriteLd, WriteLd, ReadLd]> {
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeSingleIndexedInstruction";
}
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
[], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ Sched<[WriteLd, WriteLd, ReadLd]> {
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeSingleIndexedInstruction";
}
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
[], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ Sched<[WriteLd, WriteLd, ReadLd]> {
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeSingleIndexedInstruction";
}
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
[], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ Sched<[WriteLd, WriteLd, ReadLd]> {
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeSingleIndexedInstruction";
}
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldrsw\t$Rt, [$Rn], $SImm9",
[], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ Sched<[WriteLd, WriteLd, ReadLd]> {
let mayLoad = 1;
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeSingleIndexedInstruction";
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldrsw\t$Rt, [$Rn, $SImm9]!",
[], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ Sched<[WriteLd, WriteLd, ReadLd]> {
let mayLoad = 1;
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeSingleIndexedInstruction";
(outs SomeReg:$Rt, SomeReg:$Rt2),
(ins GPR64xsp:$Rn, simm7:$SImm7),
"ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ Sched<[WriteLd, WriteLd, ReadLd]> {
let mayLoad = 1;
let DecoderMethod = "DecodeLDSTPairInstruction";
}
GPR64xsp:$Rn,
simm7:$SImm7),
"stp\t$Rt, $Rt2, [$Rn], $SImm7",
- [], NoItinerary> {
+ [], NoItinerary>,
+ Sched<[WriteSt, ReadSt, ReadSt, ReadSt]> {
let mayStore = 1;
let Constraints = "$Rn = $Rn_wb";
(ins GPR64xsp:$Rn, simm7:$SImm7),
"ldp\t$Rt, $Rt2, [$Rn], $SImm7",
[], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ Sched<[WriteLd, WriteLd, WriteLd, ReadLd]> {
let mayLoad = 1;
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeLDSTPairInstruction";
}
def _PreInd_STR : A64I_LSPpreind<opc, v, 0b0, (outs GPR64xsp:$Rn_wb),
- (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
- "stp\t$Rt, $Rt2, [$Rn, $SImm7]!",
- [], NoItinerary> {
+ (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
+ "stp\t$Rt, $Rt2, [$Rn, $SImm7]!",
+ [], NoItinerary>,
+ Sched<[WriteSt, ReadSt, ReadSt, ReadSt]> {
let mayStore = 1;
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeLDSTPairInstruction";
(ins GPR64xsp:$Rn, simm7:$SImm7),
"ldp\t$Rt, $Rt2, [$Rn, $SImm7]!",
[], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ Sched<[WriteLd, WriteLd, WriteLd, ReadLd]> {
let mayLoad = 1;
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeLDSTPairInstruction";
}
def _NonTemp_STR : A64I_LSPnontemp<opc, v, 0b0, (outs),
- (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
- "stnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
+ (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
+ "stnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
+ Sched<[WriteSt, ReadSt, ReadSt, ReadSt]> {
let mayStore = 1;
let DecoderMethod = "DecodeLDSTPairInstruction";
}
(outs SomeReg:$Rt, SomeReg:$Rt2),
(ins GPR64xsp:$Rn, simm7:$SImm7),
"ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ Sched<[WriteLd, WriteLd, ReadLd]> {
let mayLoad = 1;
let DecoderMethod = "DecodeLDSTPairInstruction";
}
(outs GPR64:$Rt, GPR64:$Rt2),
(ins GPR64xsp:$Rn, word_simm7:$SImm7),
"ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ Sched<[WriteLd, WriteLd, ReadLd]> {
let mayLoad = 1;
let DecoderMethod = "DecodeLDSTPairInstruction";
}
(outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),
(ins GPR64xsp:$Rn, word_simm7:$SImm7),
"ldpsw\t$Rt, $Rt2, [$Rn], $SImm7",
- [], NoItinerary> {
+ [], NoItinerary>,
+ Sched<[WriteLd, WriteLd, WriteLd, ReadLd]> {
let mayLoad = 1;
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeLDSTPairInstruction";
(ins GPR64xsp:$Rn, word_simm7:$SImm7),
"ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]!",
[], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ Sched<[WriteLd, WriteLd, WriteLd, ReadLd]> {
let mayLoad = 1;
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeLDSTPairInstruction";
(ins movz64_imm:$FullImm)>;
}
-let Constraints = "$src = $Rd" in
+let Constraints = "$src = $Rd",
+ SchedRW = [WriteALU, ReadALU] in
defm MOVK : A64I_movwSizes<0b11, "movk",
(ins GPR32:$src, movk32_imm:$FullImm),
(ins GPR64:$src, movk64_imm:$FullImm)>;
asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
[(set (v8i8 VPR64:$Rd),
(v8i8 (opnode8B (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
def _16B : NeonI_3VSame<0b1, u, size, opcode,
(outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
[(set (v16i8 VPR128:$Rd),
(v16i8 (opnode16B (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
}
}
asmop # "\t$Rd.4h, $Rn.4h, $Rm.4h",
[(set (v4i16 VPR64:$Rd),
(v4i16 (opnode (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
def _8H : NeonI_3VSame<0b1, u, 0b01, opcode,
(outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
asmop # "\t$Rd.8h, $Rn.8h, $Rm.8h",
[(set (v8i16 VPR128:$Rd),
(v8i16 (opnode (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
def _2S : NeonI_3VSame<0b0, u, 0b10, opcode,
(outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
[(set (v2i32 VPR64:$Rd),
(v2i32 (opnode (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
def _4S : NeonI_3VSame<0b1, u, 0b10, opcode,
(outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
[(set (v4i32 VPR128:$Rd),
(v4i32 (opnode (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
}
}
multiclass NeonI_3VSame_BHS_sizes<bit u, bits<5> opcode,
asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
[(set (v8i8 VPR64:$Rd),
(v8i8 (opnode (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
def _16B : NeonI_3VSame<0b1, u, 0b00, opcode,
(outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
[(set (v16i8 VPR128:$Rd),
(v16i8 (opnode (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
}
}
asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
[(set (v2i64 VPR128:$Rd),
(v2i64 (opnode (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
}
}
asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
[(set (ResTy2S VPR64:$Rd),
(ResTy2S (opnode (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
def _4S : NeonI_3VSame<0b1, u, {size, 0b0}, opcode,
(outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
[(set (ResTy4S VPR128:$Rd),
(ResTy4S (opnode (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
def _2D : NeonI_3VSame<0b1, u, {size, 0b1}, opcode,
(outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
[(set (ResTy2D VPR128:$Rd),
(ResTy2D (opnode (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
}
}
// Vector Multiply (Integer and Floating-Point)
+let SchedRW = [WriteFPMul, ReadFPMul, ReadFPMul] in {
defm MULvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10011, "mul", mul, 1>;
defm FMULvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11011, "fmul", fmul,
v2f32, v4f32, v2f64, 1>;
+}
// Patterns to match mul of v1i8/v1i16/v1i32 types
def : Pat<(v1i8 (mul FPR8:$Rn, FPR8:$Rm)),
// Vector Multiply (Polynomial)
+let SchedRW = [WriteFPMul, ReadFPMul, ReadFPMul] in {
defm PMULvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b10011, "pmul",
int_arm_neon_vmulp, int_arm_neon_vmulp, 1>;
+}
// Vector Multiply-accumulate and Multiply-subtract (Integer)
asmop # "\t$Rd" # asmlane # ", $Rn" # asmlane # ", $Rm" # asmlane,
[(set (OpTy VPRC:$Rd),
(OpTy (opnode (OpTy VPRC:$src), (OpTy VPRC:$Rn), (OpTy VPRC:$Rm))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU, ReadFPALU]> {
let Constraints = "$src = $Rd";
}
(sub node:$Ra, (mul node:$Rn, node:$Rm))>;
+let SchedRW = [WriteFPMAC, ReadFPMAC, ReadFPMAC] in {
def MLAvvv_8B: NeonI_3VSame_Constraint_impl<"mla", ".8b", VPR64, v8i8,
0b0, 0b0, 0b00, 0b10010, Neon_mla>;
def MLAvvv_16B: NeonI_3VSame_Constraint_impl<"mla", ".16b", VPR128, v16i8,
0b0, 0b1, 0b10, 0b10010, Neon_mls>;
def MLSvvv_4S: NeonI_3VSame_Constraint_impl<"mls", ".4s", VPR128, v4i32,
0b1, 0b1, 0b10, 0b10010, Neon_mls>;
+}
// Vector Multiply-accumulate and Multiply-subtract (Floating Point)
def Neon_fmls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
(fsub node:$Ra, (fmul_su node:$Rn, node:$Rm))>;
-let Predicates = [HasNEON, UseFusedMAC] in {
+let Predicates = [HasNEON, UseFusedMAC],
+ SchedRW = [WriteFPMAC, ReadFPMAC, ReadFPMAC] in {
def FMLAvvv_2S: NeonI_3VSame_Constraint_impl<"fmla", ".2s", VPR64, v2f32,
0b0, 0b0, 0b00, 0b11001, Neon_fmla>;
def FMLAvvv_4S: NeonI_3VSame_Constraint_impl<"fmla", ".4s", VPR128, v4f32,
// Vector Divide (Floating-Point)
+let SchedRW = [WriteFPDiv, ReadFPDiv, ReadFPDiv] in {
defm FDIVvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11111, "fdiv", fdiv,
v2f32, v4f32, v2f64, 0>;
+}
// Vector Bitwise Operations
asmop # "\t$Rd.8b, $Rn.8b, $Imm",
[(set (v8i8 VPR64:$Rd),
(v8i8 (Neon_cmpz (v8i8 VPR64:$Rn), (i32 imm:$Imm), CC)))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def _16B : NeonI_2VMisc<0b1, u, 0b00, opcode,
(outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
asmop # "\t$Rd.16b, $Rn.16b, $Imm",
[(set (v16i8 VPR128:$Rd),
(v16i8 (Neon_cmpz (v16i8 VPR128:$Rn), (i32 imm:$Imm), CC)))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def _4H : NeonI_2VMisc<0b0, u, 0b01, opcode,
(outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
asmop # "\t$Rd.4h, $Rn.4h, $Imm",
[(set (v4i16 VPR64:$Rd),
(v4i16 (Neon_cmpz (v4i16 VPR64:$Rn), (i32 imm:$Imm), CC)))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def _8H : NeonI_2VMisc<0b1, u, 0b01, opcode,
(outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
asmop # "\t$Rd.8h, $Rn.8h, $Imm",
[(set (v8i16 VPR128:$Rd),
(v8i16 (Neon_cmpz (v8i16 VPR128:$Rn), (i32 imm:$Imm), CC)))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def _2S : NeonI_2VMisc<0b0, u, 0b10, opcode,
(outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
asmop # "\t$Rd.2s, $Rn.2s, $Imm",
[(set (v2i32 VPR64:$Rd),
(v2i32 (Neon_cmpz (v2i32 VPR64:$Rn), (i32 imm:$Imm), CC)))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def _4S : NeonI_2VMisc<0b1, u, 0b10, opcode,
(outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
asmop # "\t$Rd.4s, $Rn.4s, $Imm",
[(set (v4i32 VPR128:$Rd),
(v4i32 (Neon_cmpz (v4i32 VPR128:$Rn), (i32 imm:$Imm), CC)))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def _2D : NeonI_2VMisc<0b1, u, 0b11, opcode,
(outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
asmop # "\t$Rd.2d, $Rn.2d, $Imm",
[(set (v2i64 VPR128:$Rd),
(v2i64 (Neon_cmpz (v2i64 VPR128:$Rn), (i32 imm:$Imm), CC)))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
}
// Vector Compare Mask Equal to Zero (Integer)
asmop # "\t$Rd.2s, $Rn.2s, $FPImm",
[(set (v2i32 VPR64:$Rd),
(v2i32 (Neon_cmpz (v2f32 VPR64:$Rn), (f32 fpzz32:$FPImm), CC)))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def _4S : NeonI_2VMisc<0b1, u, {size, 0b0}, opcode,
(outs VPR128:$Rd), (ins VPR128:$Rn, fpzz32:$FPImm),
asmop # "\t$Rd.4s, $Rn.4s, $FPImm",
[(set (v4i32 VPR128:$Rd),
(v4i32 (Neon_cmpz (v4f32 VPR128:$Rn), (f32 fpzz32:$FPImm), CC)))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def _2D : NeonI_2VMisc<0b1, u, {size, 0b1}, opcode,
(outs VPR128:$Rd), (ins VPR128:$Rn, fpzz32:$FPImm),
asmop # "\t$Rd.2d, $Rn.2d, $FPImm",
[(set (v2i64 VPR128:$Rd),
(v2i64 (Neon_cmpz (v2f64 VPR128:$Rn), (f32 fpzz32:$FPImm), CC)))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
}
// Vector Compare Mask Equal to Zero (Floating Point)
int_arm_neon_vpadd,
v2f32, v4f32, v2f64, 1>;
+let SchedRW = [WriteFPMul, ReadFPMul, ReadFPMul] in {
// Vector Saturating Doubling Multiply High
defm SQDMULHvvv : NeonI_3VSame_HS_sizes<0b0, 0b10110, "sqdmulh",
int_arm_neon_vqdmulh, 1>;
defm FMULXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11011, "fmulx",
int_aarch64_neon_vmulx,
v2f32, v4f32, v2f64, 1>;
+}
// Patterns to match llvm.aarch64.* intrinsic for
// ADDP, SMINP, UMINP, SMAXP, UMAXP having i32 as output
[(set (v2i32 VPR64:$Rd),
(v2i32 (opnode (timm:$Imm),
(neon_mov_imm_LSL_operand:$Simm))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU]> {
bits<2> Simm;
let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
}
[(set (v4i32 VPR128:$Rd),
(v4i32 (opnode (timm:$Imm),
(neon_mov_imm_LSL_operand:$Simm))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU]> {
bits<2> Simm;
let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
}
[(set (v4i16 VPR64:$Rd),
(v4i16 (opnode (timm:$Imm),
(neon_mov_imm_LSLH_operand:$Simm))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU]> {
bit Simm;
let cmode = {0b1, 0b0, Simm, 0b0};
}
[(set (v8i16 VPR128:$Rd),
(v8i16 (opnode (timm:$Imm),
(neon_mov_imm_LSLH_operand:$Simm))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU]> {
bit Simm;
let cmode = {0b1, 0b0, Simm, 0b0};
}
(v2i32 (opnode (v2i32 VPR64:$src),
(v2i32 (neonopnode timm:$Imm,
neon_mov_imm_LSL_operand:$Simm)))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]> {
bits<2> Simm;
let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
}
(v4i32 (opnode (v4i32 VPR128:$src),
(v4i32 (neonopnode timm:$Imm,
neon_mov_imm_LSL_operand:$Simm)))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]> {
bits<2> Simm;
let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
}
(v4i16 (opnode (v4i16 VPR64:$src),
(v4i16 (neonopnode timm:$Imm,
neon_mov_imm_LSL_operand:$Simm)))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]> {
bit Simm;
let cmode = {0b1, 0b0, Simm, 0b1};
}
(v8i16 (opnode (v8i16 VPR128:$src),
(v8i16 (neonopnode timm:$Imm,
neon_mov_imm_LSL_operand:$Simm)))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]> {
bit Simm;
let cmode = {0b1, 0b0, Simm, 0b1};
}
[(set (v2i32 VPR64:$Rd),
(v2i32 (opnode (timm:$Imm),
(neon_mov_imm_MSL_operand:$Simm))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU]> {
bit Simm;
let cmode = {0b1, 0b1, 0b0, Simm};
}
[(set (v4i32 VPR128:$Rd),
(v4i32 (opnode (timm:$Imm),
(neon_mov_imm_MSL_operand:$Simm))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU]> {
bit Simm;
let cmode = {0b1, 0b1, 0b0, Simm};
}
"movi\t$Rd.8b, $Imm",
[(set (v8i8 VPR64:$Rd),
(v8i8 (Neon_movi (timm:$Imm), (i32 imm))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU]> {
let cmode = 0b1110;
}
"movi\t$Rd.16b, $Imm",
[(set (v16i8 VPR128:$Rd),
(v16i8 (Neon_movi (timm:$Imm), (i32 imm))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU]> {
let cmode = 0b1110;
}
}
"movi\t $Rd.2d, $Imm",
[(set (v2i64 VPR128:$Rd),
(v2i64 (Neon_movi (timm:$Imm), (i32 imm))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU]> {
let cmode = 0b1110;
}
}
"movi\t $Rd, $Imm",
[(set (v1i64 FPR64:$Rd),
(v1i64 (Neon_movi (timm:$Imm), (i32 imm))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU]> {
let cmode = 0b1110;
}
}
"fmov\t$Rd" # asmlane # ", $Imm",
[(set (OpTy VPRC:$Rd),
(OpTy (Neon_fmovi (timm:$Imm))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU]> {
let cmode = 0b1111;
}
[(set (Ty VPRC:$Rd),
(Ty (OpNode (Ty VPRC:$Rn),
(Ty (Neon_vdup (i32 ImmTy:$Imm))))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
multiclass NeonI_N2VShL<bit u, bits<5> opcode, string asmop> {
// 64-bit vector types.
(DestTy (shl
(DestTy (ExtOp (SrcTy VPR64:$Rn))),
(DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
class N2VShiftLongHigh<bit q, bit u, bits<5> opcode, string asmop, string DestT,
string SrcT, ValueType DestTy, ValueType SrcTy,
(DestTy (ExtOp
(SrcTy (getTop VPR128:$Rn)))),
(DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
multiclass NeonI_N2VShLL<string prefix, bit u, bits<5> opcode, string asmop,
SDNode ExtOp> {
asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
[(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$Rn),
(i32 ImmTy:$Imm))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
// shift right (vector by immediate)
multiclass NeonI_N2VShR_RQ<bit u, bits<5> opcode, string asmop,
[(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
(Ty (OpNode (Ty VPRC:$Rn),
(Ty (Neon_vdup (i32 ImmTy:$Imm))))))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
let Constraints = "$src = $Rd";
}
asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
[(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
(Ty (OpNode (Ty VPRC:$Rn), (i32 ImmTy:$Imm))))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
let Constraints = "$src = $Rd";
}
asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
[(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$src), (Ty VPRC:$Rn),
(i32 ImmTy:$Imm))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
let Constraints = "$src = $Rd";
}
: NeonI_2VShiftImm<q, u, opcode,
(outs VPR64:$Rd), (ins VPR128:$Rn, ImmTy:$Imm),
asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
class N2VShR_Narrow_Hi<bit q, bit u, bits<5> opcode, string asmop, string DestT,
string SrcT, Operand ImmTy>
: NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
(ins VPR128:$src, VPR128:$Rn, ImmTy:$Imm),
asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
- [], NoItinerary> {
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
let Constraints = "$src = $Rd";
}
asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
[(set (DestTy VPRC:$Rd), (DestTy (IntOp (SrcTy VPRC:$Rn),
(i32 ImmTy:$Imm))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
multiclass NeonI_N2VCvt_Fx2fp<bit u, bits<5> opcode, string asmop,
SDPatternOperator IntOp> {
asmop # "\t$Rd, $Rn.8b",
[(set (v1i16 FPR16:$Rd),
(v1i16 (opnode (v8i8 VPR64:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def _1h16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
(outs FPR16:$Rd), (ins VPR128:$Rn),
asmop # "\t$Rd, $Rn.16b",
[(set (v1i16 FPR16:$Rd),
(v1i16 (opnode (v16i8 VPR128:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def _1s4h: NeonI_2VAcross<0b0, u, 0b01, opcode,
(outs FPR32:$Rd), (ins VPR64:$Rn),
asmop # "\t$Rd, $Rn.4h",
[(set (v1i32 FPR32:$Rd),
(v1i32 (opnode (v4i16 VPR64:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def _1s8h: NeonI_2VAcross<0b1, u, 0b01, opcode,
(outs FPR32:$Rd), (ins VPR128:$Rn),
asmop # "\t$Rd, $Rn.8h",
[(set (v1i32 FPR32:$Rd),
(v1i32 (opnode (v8i16 VPR128:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
// _1d2s doesn't exist!
asmop # "\t$Rd, $Rn.4s",
[(set (v1i64 FPR64:$Rd),
(v1i64 (opnode (v4i32 VPR128:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
}
defm SADDLV : NeonI_2VAcross_1<0b0, 0b00011, "saddlv", int_aarch64_neon_saddlv>;
asmop # "\t$Rd, $Rn.8b",
[(set (v1i8 FPR8:$Rd),
(v1i8 (opnode (v8i8 VPR64:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def _1b16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
(outs FPR8:$Rd), (ins VPR128:$Rn),
asmop # "\t$Rd, $Rn.16b",
[(set (v1i8 FPR8:$Rd),
(v1i8 (opnode (v16i8 VPR128:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def _1h4h: NeonI_2VAcross<0b0, u, 0b01, opcode,
(outs FPR16:$Rd), (ins VPR64:$Rn),
asmop # "\t$Rd, $Rn.4h",
[(set (v1i16 FPR16:$Rd),
(v1i16 (opnode (v4i16 VPR64:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def _1h8h: NeonI_2VAcross<0b1, u, 0b01, opcode,
(outs FPR16:$Rd), (ins VPR128:$Rn),
asmop # "\t$Rd, $Rn.8h",
[(set (v1i16 FPR16:$Rd),
(v1i16 (opnode (v8i16 VPR128:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
// _1s2s doesn't exist!
asmop # "\t$Rd, $Rn.4s",
[(set (v1i32 FPR32:$Rd),
(v1i32 (opnode (v4i32 VPR128:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
}
defm SMAXV : NeonI_2VAcross_2<0b0, 0b01010, "smaxv", int_aarch64_neon_smaxv>;
asmop # "\t$Rd, $Rn.4s",
[(set (f32 FPR32:$Rd),
(f32 (opnode (v4f32 VPR128:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
}
defm FMAXNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b00, "fmaxnmv",
asmop # "\t$Rd." # OpS # ", $Rn." # OpS # ", $Rm." # OpS,
[(set (Ty OpVPR:$Rd),
(Ty (opnode (Ty OpVPR:$Rn), (Ty OpVPR:$Rm))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
multiclass NeonI_Perm_pat<bits<3> opcode, string asmop,
SDPatternOperator opnode> {
[(set (ResTy VPR128:$Rd),
(ResTy (opnode (ResTy (ext (OpTy OpVPR:$Rn))),
(ResTy (ext (OpTy OpVPR:$Rm))))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
multiclass NeonI_3VDL_s<bit u, bits<4> opcode,
string asmop, SDPatternOperator opnode,
[(set (ResTy VPR128:$Rd),
(ResTy (opnode (ResTy VPR128:$Rn),
(ResTy (ext (OpTy OpVPR:$Rm))))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
multiclass NeonI_3VDW_s<bit u, bits<4> opcode, string asmop,
SDPatternOperator opnode> {
(ResTy (get_hi
(OpTy (opnode (OpTy VPR128:$Rn),
(OpTy VPR128:$Rm))))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
multiclass NeonI_3VDN_addhn_2Op<bit u, bits<4> opcode, string asmop,
SDPatternOperator opnode, bit Commutable = 0> {
asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
[(set (ResTy ResVPR:$Rd),
(ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
// normal narrow pattern
multiclass NeonI_3VDN_2Op<bit u, bits<4> opcode, string asmop,
: NeonI_3VDiff<q, u, size, opcode,
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
- [], NoItinerary> {
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU, ReadFPALU]> {
let Constraints = "$src = $Rd";
let neverHasSideEffects = 1;
}
[(set (ResTy VPR128:$Rd),
(ResTy (zext (OpSTy (opnode (OpTy OpVPR:$Rn),
(OpTy OpVPR:$Rm))))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
multiclass NeonI_3VDL_zext<bit u, bits<4> opcode, string asmop,
SDPatternOperator opnode, bit Commutable = 0> {
(ResTy VPR128:$src),
(ResTy (zext (OpSTy (subop (OpTy OpVPR:$Rn),
(OpTy OpVPR:$Rm))))))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU, ReadFPALU]> {
let Constraints = "$src = $Rd";
}
// Long pattern with 2 operands
multiclass NeonI_3VDL_2Op<bit u, bits<4> opcode, string asmop,
SDPatternOperator opnode, bit Commutable = 0> {
- let isCommutable = Commutable in {
+ let isCommutable = Commutable,
+ SchedRW = [WriteFPMul, ReadFPMul, ReadFPMul] in {
def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
opnode, VPR128, VPR64, v8i16, v8i8>;
def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
[(set (ResTy VPR128:$Rd),
(ResTy (opnode (OpTy VPR128:$Rn), (OpTy VPR128:$Rm))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPMul, ReadFPMul, ReadFPMul]>;
multiclass NeonI_3VDL2_2Op_mull_v1<bit u, bits<4> opcode, string asmop,
string opnode, bit Commutable = 0> {
(ResTy (opnode
(ResTy VPR128:$src),
(OpTy VPR64:$Rn), (OpTy VPR64:$Rm))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPMAC, ReadFPMAC, ReadFPMAC, ReadFPMAC]> {
let Constraints = "$src = $Rd";
}
(ResTy (subop
(ResTy VPR128:$src),
(ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPMAC, ReadFPMAC, ReadFPMAC, ReadFPMAC]> {
let Constraints = "$src = $Rd";
}
}
}
+let SchedRW = [WriteFPMul, ReadFPMul, ReadFPMul] in {
defm SQDMULLvvv : NeonI_3VDL_v2<0b0, 0b1101, "sqdmull",
int_arm_neon_vqdmull, 1>;
+}
multiclass NeonI_3VDL2_2Op_mull_v2<bit u, bits<4> opcode, string asmop,
string opnode, bit Commutable = 0> {
}
}
+let SchedRW = [WriteFPMul, ReadFPMul, ReadFPMul] in
defm PMULLvvv : NeonI_3VDL_v3<0b0, 0b1110, "pmull", int_arm_neon_vmullp,
int_aarch64_neon_vmull_p64, 1>;
(i64 (vector_extract (v2i64 VPR128:$Rn), 1)))),
(v1i64 (scalar_to_vector
(i64 (vector_extract (v2i64 VPR128:$Rm), 1)))))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPMul, ReadFPMul, ReadFPMul]>;
}
def : Pat<(v16i8 (int_aarch64_neon_vmull_p64
(outs VecList:$Rt), (ins GPR64xsp:$Rn),
asmop # "\t$Rt, [$Rn]",
[],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteVecLd, ReadVecLd]> {
let mayLoad = 1;
let neverHasSideEffects = 1;
}
(outs), (ins GPR64xsp:$Rn, VecList:$Rt),
asmop # "\t$Rt, [$Rn]",
[],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteVecSt, ReadVecSt, ReadVecSt]> {
let mayStore = 1;
let neverHasSideEffects = 1;
}
(ins GPR64xsp:$Rn, ImmTy:$amt),
asmop # "\t$Rt, [$Rn], $amt",
[],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteVecLd, WriteVecLd, ReadVecLd]> {
let Rm = 0b11111;
}
(ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
asmop # "\t$Rt, [$Rn], $Rm",
[],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteVecLd, WriteVecLd, ReadVecLd, ReadVecLd]>;
}
}
(ins GPR64xsp:$Rn, ImmTy:$amt, VecList:$Rt),
asmop # "\t$Rt, [$Rn], $amt",
[],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteVecSt, ReadVecSt, ReadVecSt]> {
let Rm = 0b11111;
}
(ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VecList:$Rt),
asmop # "\t$Rt, [$Rn], $Rm",
[],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteVecSt, ReadVecSt, ReadVecSt, ReadVecSt]>;
}
}
(outs VecList:$Rt), (ins GPR64xsp:$Rn),
asmop # "\t$Rt, [$Rn]",
[],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteVecLd, ReadVecLd]> {
let mayLoad = 1;
let neverHasSideEffects = 1;
}
(ins GPR64xsp:$Rn, VList:$src, ImmOp:$lane),
asmop # "\t$Rt[$lane], [$Rn]",
[],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteVecLd, ReadVecLd, ReadVecLd]> {
let mayLoad = 1;
let neverHasSideEffects = 1;
let hasExtraDefRegAllocReq = 1;
(outs), (ins GPR64xsp:$Rn, VList:$Rt, ImmOp:$lane),
asmop # "\t$Rt[$lane], [$Rn]",
[],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteVecSt, ReadVecSt, ReadVecSt]> {
let mayStore = 1;
let neverHasSideEffects = 1;
let hasExtraDefRegAllocReq = 1;
(ins GPR64xsp:$Rn, ImmTy:$amt),
asmop # "\t$Rt, [$Rn], $amt",
[],
- NoItinerary> {
- let Rm = 0b11111;
- }
+ NoItinerary>,
+ Sched<[WriteVecLd, WriteVecLd, ReadVecLd]> {
+ let Rm = 0b11111;
+ }
def _register : NeonI_LdOne_Dup_Post<q, r, opcode, size,
(outs VecList:$Rt, GPR64xsp:$wb),
(ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
asmop # "\t$Rt, [$Rn], $Rm",
[],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteVecLd, WriteVecLd, ReadVecLd, ReadVecLd]>;
}
}
VList:$src, ImmOp:$lane),
asmop # "\t$Rt[$lane], [$Rn], $amt",
[],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteVecLd, WriteVecLd, ReadVecLd, ReadVecLd]> {
let Rm = 0b11111;
}
VList:$src, ImmOp:$lane),
asmop # "\t$Rt[$lane], [$Rn], $Rm",
[],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteVecLd, WriteVecLd, ReadVecLd, ReadVecLd, ReadVecLd]>;
}
multiclass LD_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
VList:$Rt, ImmOp:$lane),
asmop # "\t$Rt[$lane], [$Rn], $amt",
[],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteVecSt, ReadVecSt, ReadVecSt]> {
let Rm = 0b11111;
}
ImmOp:$lane),
asmop # "\t$Rt[$lane], [$Rn], $Rm",
[],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteVecSt, ReadVecSt, ReadVecSt, ReadVecSt]>;
}
multiclass ST_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
(outs FPRC:$Rd), (ins FPRC:$Rn, FPRC:$Rm),
!strconcat(asmop, "\t$Rd, $Rn, $Rm"),
[],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
class NeonI_Scalar3Same_D_size<bit u, bits<5> opcode, string asmop>
: NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
(outs FPRCD:$Rd), (ins FPRCS:$Rn, FPRCS:$Rm),
!strconcat(asmop, "\t$Rd, $Rn, $Rm"),
[],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
multiclass NeonI_Scalar3Diff_HS_size<bit u, bits<4> opcode, string asmop> {
def shh : NeonI_Scalar3Diff_size<u, 0b01, opcode, asmop, FPR32, FPR16>;
(outs FPR32:$Rd), (ins FPR32:$Src, FPR16:$Rn, FPR16:$Rm),
!strconcat(asmop, "\t$Rd, $Rn, $Rm"),
[],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU, ReadFPALU]>;
def dss : NeonI_Scalar3Diff<u, 0b10, opcode,
(outs FPR64:$Rd), (ins FPR64:$Src, FPR32:$Rn, FPR32:$Rm),
!strconcat(asmop, "\t$Rd, $Rn, $Rm"),
[],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU, ReadFPALU]>;
}
}
(outs FPRCD:$Rd), (ins FPRCS:$Rn),
!strconcat(asmop, "\t$Rd, $Rn"),
[],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
multiclass NeonI_Scalar2SameMisc_SD_size<bit u, bit size_high, bits<5> opcode,
string asmop> {
(outs FPRC:$Rd), (ins FPRC:$Src, FPRC:$Rn),
!strconcat(asmop, "\t$Rd, $Rn"),
[],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
multiclass NeonI_Scalar2SameMisc_accum_BHSD_size<bit u, bits<5> opcode,
string asmop> {
(outs FPR64:$Rd), (ins FPR64:$Rn, neon_uimm0:$Imm),
!strconcat(asmop, "\t$Rd, $Rn, $Imm"),
[],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
multiclass NeonI_Scalar2SameMisc_cmpz_SD_size<bit u, bits<5> opcode,
string asmop> {
(outs FPR32:$Rd), (ins FPR32:$Rn, fpzz32:$FPImm),
!strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
[],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def ddi : NeonI_Scalar2SameMisc<u, 0b11, opcode,
(outs FPR64:$Rd), (ins FPR64:$Rn, fpzz32:$FPImm),
!strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
[],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
}
class Neon_Scalar2SameMisc_cmpz_D_size_patterns<SDPatternOperator opnode,
: NeonI_ScalarShiftImm<u, opcode,
(outs FPRC:$Rd), (ins FPRC:$Rn, ImmTy:$Imm),
!strconcat(asmop, "\t$Rd, $Rn, $Imm"),
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
multiclass NeonI_ScalarShiftRightImm_D_size<bit u, bits<5> opcode,
string asmop> {
(outs FPR64:$Rd),
(ins FPR64:$Src, FPR64:$Rn, shr_imm64:$Imm),
!strconcat(asmop, "\t$Rd, $Rn, $Imm"),
- [], NoItinerary> {
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
bits<6> Imm;
let Inst{22} = 0b1; // immh:immb = 1xxxxxx
let Inst{21-16} = Imm;
(outs FPR64:$Rd),
(ins FPR64:$Src, FPR64:$Rn, shl_imm64:$Imm),
!strconcat(asmop, "\t$Rd, $Rn, $Imm"),
- [], NoItinerary> {
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
bits<6> Imm;
let Inst{22} = 0b1; // immh:immb = 1xxxxxx
let Inst{21-16} = Imm;
: NeonI_ScalarShiftImm<u, opcode,
(outs FPRCD:$Rd), (ins FPRCS:$Rn, ImmTy:$Imm),
!strconcat(asmop, "\t$Rd, $Rn, $Imm"),
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
multiclass NeonI_ScalarShiftImm_narrow_HSD_size<bit u, bits<5> opcode,
string asmop> {
UQSUBhhh, UQSUBsss, UQSUBddd>;
// Scalar Integer Saturating Doubling Multiply Half High
+let SchedRW = [WriteFPMul, ReadFPMul, ReadFPMul, ReadFPMul] in
defm SQDMULH : NeonI_Scalar3Same_HS_sizes<0b0, 0b10110, "sqdmulh", 1>;
// Scalar Integer Saturating Rounding Doubling Multiply Half High
+let SchedRW = [WriteFPMul, ReadFPMul, ReadFPMul] in {
defm SQRDMULH : NeonI_Scalar3Same_HS_sizes<0b1, 0b10110, "sqrdmulh", 1>;
+}
// Patterns to match llvm.arm.* intrinsic for
// Scalar Integer Saturating Doubling Multiply Half High and
defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqrdmulh, SQRDMULHhhh,
SQRDMULHsss>;
+let SchedRW = [WriteFPMul, ReadFPMul, ReadFPMul, ReadFPMul] in {
// Scalar Floating-point Multiply Extended
defm FMULX : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11011, "fmulx", 1>;
+}
// Scalar Floating-point Reciprocal Step
defm FRECPS : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11111, "frecps", 0>;
defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshifts, SQRSHLddd>;
defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshiftu, UQRSHLddd>;
+let SchedRW = [WriteFPMAC, ReadFPMAC, ReadFPMAC, ReadFPMAC] in {
// Signed Saturating Doubling Multiply-Add Long
defm SQDMLAL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1001, "sqdmlal">;
+}
defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlal,
SQDMLALshh, SQDMLALdss>;
// Signed Saturating Doubling Multiply-Subtract Long
+let SchedRW = [WriteFPMAC, ReadFPMAC, ReadFPMAC, ReadFPMAC] in {
defm SQDMLSL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1011, "sqdmlsl">;
+}
defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlsl,
SQDMLSLshh, SQDMLSLdss>;
// Signed Saturating Doubling Multiply Long
+let SchedRW = [WriteFPMul, ReadFPMul, ReadFPMul, ReadFPMul] in {
defm SQDMULL : NeonI_Scalar3Diff_HS_size<0b0, 0b1101, "sqdmull">;
+}
defm : Neon_Scalar3Diff_HS_size_patterns<int_arm_neon_vqdmull,
SQDMULLshh, SQDMULLdss>;
(outs FPR64:$Rd), (ins VPR128:$Rn),
!strconcat(asmop, "\t$Rd, $Rn.2d"),
[],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
}
}
(outs FPR32:$Rd), (ins VPR64:$Rn),
!strconcat(asmop, "\t$Rd, $Rn.2s"),
[],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
}
}
(ins OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
[],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPMul, ReadFPMul, ReadFPMul]> {
bits<3> Imm;
bits<5> MRm;
}
(ins ResFPR:$src, OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
[],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPMAC, ReadFPMAC, ReadFPMAC, ReadFPMAC]> {
let Constraints = "$src = $Rd";
bits<3> Imm;
bits<5> MRm;
: NeonI_ScalarCopy<(outs ResRC:$Rd), (ins VPRC:$Rn, OpImm:$Imm),
asmop # "\t$Rd, $Rn." # asmlane # "[$Imm]",
[],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]> {
bits<4> Imm;
}
asmop # "\t$Rd." # OpS # ", $Rn." # OpS #
", $Rm." # OpS # ", $Index",
[],
- NoItinerary>{
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>{
bits<4> Index;
}
(outs OpVPR:$Rd), (ins VecList:$Rn, OpVPR:$Rm),
asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
[],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
// The vectors in look up table are always 16b
multiclass NI_TBL_pat<bits<2> len, bit op, string asmop, string List> {
(outs OpVPR:$Rd), (ins OpVPR:$src, VecList:$Rn, OpVPR:$Rm),
asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
[],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU, ReadFPALU]> {
let Constraints = "$src = $Rd";
}
(ResTy VPR128:$src),
(OpTy OpGPR:$Rn),
(OpImm:$Imm))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
bits<4> Imm;
let Constraints = "$src = $Rd";
}
ResImm:$Immd, ResImm:$Immn),
asmop # "\t$Rd." # Res # "[$Immd], $Rn." # Res # "[$Immn]",
[],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
let Constraints = "$src = $Rd";
bits<4> Immd;
bits<4> Immn;
(ResTy (vector_extract
(OpTy VPR128:$Rn), (OpImm:$Imm))),
eleTy)))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]> {
bits<4> Imm;
}
[(set (ResTy ResGPR:$Rd),
(ResTy (vector_extract
(OpTy VPR128:$Rn), (OpImm:$Imm))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]> {
bits<4> Imm;
}
(ins VPR128:$Rn, OpImm:$Imm),
asmop # "\t$Rd" # rdlane # ", $Rn" # rnlane # "[$Imm]",
[],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]> {
bits<4> Imm;
}
asmop # "\t$Rd" # rdlane # ", $Rn",
[(set (ResTy ResVPR:$Rd),
(ResTy (Neon_vdup (OpTy OpGPR:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def DUP16b : NeonI_DUP<0b1, "dup", ".16b", VPR128, v16i8, GPR32, i32> {
let Inst{20-16} = 0b00001;
asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
", $Re." # EleOpS # "[$Index]",
[],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPMAC, ReadFPMAC, ReadFPMAC, ReadFPMAC]> {
bits<3> Index;
bits<5> Re;
asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
", $Re." # EleOpS # "[$Index]",
[],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
bits<3> Index;
bits<5> Re;
}
}
}
+let SchedRW = [WriteFPMul, ReadFPMul, ReadFPMul] in {
defm MULve : NI_2VE_v1_2op<0b0, 0b1000, "mul">;
defm SQDMULHve : NI_2VE_v1_2op<0b0, 0b1100, "sqdmulh">;
defm SQRDMULHve : NI_2VE_v1_2op<0b0, 0b1101, "sqrdmulh">;
+}
// Pattern for lane in 128-bit vector
class NI_2VE_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
}
}
+let SchedRW = [WriteFPMul, ReadFPMul, ReadFPMul] in {
defm FMULve : NI_2VE_v2_2op<0b0, 0b1001, "fmul">;
defm FMULXve : NI_2VE_v2_2op<0b1, 0b1001, "fmulx">;
+}
class NI_2VE_mul_lane_2d<Instruction INST, Operand OpImm, SDPatternOperator op,
RegisterOperand OpVPR, RegisterOperand EleOpVPR,
}
}
+let SchedRW = [WriteFPMul, ReadFPMul, ReadFPMul] in {
defm SMULLve : NI_2VE_v3_2op<0b0, 0b1010, "smull">;
defm UMULLve : NI_2VE_v3_2op<0b1, 0b1010, "umull">;
defm SQDMULLve : NI_2VE_v3_2op<0b0, 0b1011, "sqdmull">;
+}
def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
(FMOVdd $src)>;
asmop # "\t$Rd." # Res # ", $Rn." # Res,
[(set (ResTy ResVPR:$Rd),
(ResTy (Neon_Rev (ResTy ResVPR:$Rn))))],
- NoItinerary> ;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def REV64_16b : NeonI_REV<"rev64", "16b", 0b00, 0b1, 0b0, 0b00000, VPR128,
v16i8, Neon_rev64>;
asmop # "\t$Rd.8h, $Rn.16b",
[(set (v8i16 VPR128:$Rd),
(v8i16 (Neon_Padd (v16i8 VPR128:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
(outs VPR64:$Rd), (ins VPR64:$Rn),
asmop # "\t$Rd.4h, $Rn.8b",
[(set (v4i16 VPR64:$Rd),
(v4i16 (Neon_Padd (v8i8 VPR64:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
(outs VPR128:$Rd), (ins VPR128:$Rn),
asmop # "\t$Rd.4s, $Rn.8h",
[(set (v4i32 VPR128:$Rd),
(v4i32 (Neon_Padd (v8i16 VPR128:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
(outs VPR64:$Rd), (ins VPR64:$Rn),
asmop # "\t$Rd.2s, $Rn.4h",
[(set (v2i32 VPR64:$Rd),
(v2i32 (Neon_Padd (v4i16 VPR64:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
(outs VPR128:$Rd), (ins VPR128:$Rn),
asmop # "\t$Rd.2d, $Rn.4s",
[(set (v2i64 VPR128:$Rd),
(v2i64 (Neon_Padd (v4i32 VPR128:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
(outs VPR64:$Rd), (ins VPR64:$Rn),
asmop # "\t$Rd.1d, $Rn.2s",
[(set (v1i64 VPR64:$Rd),
(v1i64 (Neon_Padd (v2i32 VPR64:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
}
defm SADDLP : NeonI_PairwiseAdd<"saddlp", 0b0, 0b00010,
[(set (v8i16 VPR128:$Rd),
(v8i16 (Neon_Padd
(v8i16 VPR128:$src), (v16i8 VPR128:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
(outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
[(set (v4i16 VPR64:$Rd),
(v4i16 (Neon_Padd
(v4i16 VPR64:$src), (v8i8 VPR64:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
[(set (v4i32 VPR128:$Rd),
(v4i32 (Neon_Padd
(v4i32 VPR128:$src), (v8i16 VPR128:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
(outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
[(set (v2i32 VPR64:$Rd),
(v2i32 (Neon_Padd
(v2i32 VPR64:$src), (v4i16 VPR64:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
[(set (v2i64 VPR128:$Rd),
(v2i64 (Neon_Padd
(v2i64 VPR128:$src), (v4i32 VPR128:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
(outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
[(set (v1i64 VPR64:$Rd),
(v1i64 (Neon_Padd
(v1i64 VPR64:$src), (v2i32 VPR64:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
}
}
def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
(outs VPR128:$Rd), (ins VPR128:$Rn),
asmop # "\t$Rd.16b, $Rn.16b",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
(outs VPR128:$Rd), (ins VPR128:$Rn),
asmop # "\t$Rd.8h, $Rn.8h",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
(outs VPR128:$Rd), (ins VPR128:$Rn),
asmop # "\t$Rd.4s, $Rn.4s",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
(outs VPR128:$Rd), (ins VPR128:$Rn),
asmop # "\t$Rd.2d, $Rn.2d",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
(outs VPR64:$Rd), (ins VPR64:$Rn),
asmop # "\t$Rd.8b, $Rn.8b",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
(outs VPR64:$Rd), (ins VPR64:$Rn),
asmop # "\t$Rd.4h, $Rn.4h",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
(outs VPR64:$Rd), (ins VPR64:$Rn),
asmop # "\t$Rd.2s, $Rn.2s",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
}
defm SQABS : NeonI_2VMisc_BHSDsize_1Arg<"sqabs", 0b0, 0b00111>;
def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
asmop # "\t$Rd.16b, $Rn.16b",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
asmop # "\t$Rd.8h, $Rn.8h",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
asmop # "\t$Rd.4s, $Rn.4s",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
asmop # "\t$Rd.2d, $Rn.2d",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
(outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
asmop # "\t$Rd.8b, $Rn.8b",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
(outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
asmop # "\t$Rd.4h, $Rn.4h",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
(outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
asmop # "\t$Rd.2s, $Rn.2s",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
}
}
asmop # "\t$Rd.16b, $Rn.16b",
[(set (v16i8 VPR128:$Rd),
(v16i8 (Neon_Op (v16i8 VPR128:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 8h : NeonI_2VMisc<0b1, U, 0b01, 0b00100,
(outs VPR128:$Rd), (ins VPR128:$Rn),
asmop # "\t$Rd.8h, $Rn.8h",
[(set (v8i16 VPR128:$Rd),
(v8i16 (Neon_Op (v8i16 VPR128:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 4s : NeonI_2VMisc<0b1, U, 0b10, 0b00100,
(outs VPR128:$Rd), (ins VPR128:$Rn),
asmop # "\t$Rd.4s, $Rn.4s",
[(set (v4i32 VPR128:$Rd),
(v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 8b : NeonI_2VMisc<0b0, U, 0b00, 0b00100,
(outs VPR64:$Rd), (ins VPR64:$Rn),
asmop # "\t$Rd.8b, $Rn.8b",
[(set (v8i8 VPR64:$Rd),
(v8i8 (Neon_Op (v8i8 VPR64:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 4h : NeonI_2VMisc<0b0, U, 0b01, 0b00100,
(outs VPR64:$Rd), (ins VPR64:$Rn),
asmop # "\t$Rd.4h, $Rn.4h",
[(set (v4i16 VPR64:$Rd),
(v4i16 (Neon_Op (v4i16 VPR64:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 2s : NeonI_2VMisc<0b0, U, 0b10, 0b00100,
(outs VPR64:$Rd), (ins VPR64:$Rn),
asmop # "\t$Rd.2s, $Rn.2s",
[(set (v2i32 VPR64:$Rd),
(v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
}
defm CLS : NeonI_2VMisc_BHSsizes<"cls", 0b0, int_arm_neon_vcls>;
def 16b : NeonI_2VMisc<0b1, U, size, Opcode,
(outs VPR128:$Rd), (ins VPR128:$Rn),
asmop # "\t$Rd.16b, $Rn.16b",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 8b : NeonI_2VMisc<0b0, U, size, Opcode,
(outs VPR64:$Rd), (ins VPR64:$Rn),
asmop # "\t$Rd.8b, $Rn.8b",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
}
defm CNT : NeonI_2VMisc_Bsize<"cnt", 0b0, 0b00, 0b00101>;
asmop # "\t$Rd.4s, $Rn.4s",
[(set (v4f32 VPR128:$Rd),
(v4f32 (Neon_Op (v4f32 VPR128:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
(outs VPR128:$Rd), (ins VPR128:$Rn),
asmop # "\t$Rd.2d, $Rn.2d",
[(set (v2f64 VPR128:$Rd),
(v2f64 (Neon_Op (v2f64 VPR128:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
(outs VPR64:$Rd), (ins VPR64:$Rn),
asmop # "\t$Rd.2s, $Rn.2s",
[(set (v2f32 VPR64:$Rd),
(v2f32 (Neon_Op (v2f32 VPR64:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
}
defm FABS : NeonI_2VMisc_SDsizes<"fabs", 0b0, 0b01111, fabs>;
def 8h8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
(outs VPR64:$Rd), (ins VPR128:$Rn),
asmop # "\t$Rd.8b, $Rn.8h",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 4s4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
(outs VPR64:$Rd), (ins VPR128:$Rn),
asmop # "\t$Rd.4h, $Rn.4s",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 2d2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
(outs VPR64:$Rd), (ins VPR128:$Rn),
asmop # "\t$Rd.2s, $Rn.2d",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
let Constraints = "$Rd = $src" in {
def 8h16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
asmop # "2\t$Rd.16b, $Rn.8h",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
def 4s8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
asmop # "2\t$Rd.8h, $Rn.4s",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
def 2d4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
asmop # "2\t$Rd.4s, $Rn.2d",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
}
}
(outs VPR128:$Rd),
(ins VPR64:$Rn, uimm_exact8:$Imm),
asmop # "\t$Rd.8h, $Rn.8b, $Imm",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 4h4s : NeonI_2VMisc<0b0, U, 0b01, opcode,
(outs VPR128:$Rd),
(ins VPR64:$Rn, uimm_exact16:$Imm),
asmop # "\t$Rd.4s, $Rn.4h, $Imm",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 2s2d : NeonI_2VMisc<0b0, U, 0b10, opcode,
(outs VPR128:$Rd),
(ins VPR64:$Rn, uimm_exact32:$Imm),
asmop # "\t$Rd.2d, $Rn.2s, $Imm",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
(outs VPR128:$Rd),
(ins VPR128:$Rn, uimm_exact8:$Imm),
asmop # "2\t$Rd.8h, $Rn.16b, $Imm",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
(outs VPR128:$Rd),
(ins VPR128:$Rn, uimm_exact16:$Imm),
asmop # "2\t$Rd.4s, $Rn.8h, $Imm",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
(outs VPR128:$Rd),
(ins VPR128:$Rn, uimm_exact32:$Imm),
asmop # "2\t$Rd.2d, $Rn.4s, $Imm",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
}
}
def 4s4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
(outs VPR64:$Rd), (ins VPR128:$Rn),
asmop # "\t$Rd.4h, $Rn.4s",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
(outs VPR64:$Rd), (ins VPR128:$Rn),
asmop # "\t$Rd.2s, $Rn.2d",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
let Constraints = "$src = $Rd" in {
def 4s8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
asmop # "2\t$Rd.8h, $Rn.4s",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
asmop # "2\t$Rd.4s, $Rn.2d",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
}
}
def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
(outs VPR64:$Rd), (ins VPR128:$Rn),
asmop # "\t$Rd.2s, $Rn.2d",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
asmop # "2\t$Rd.4s, $Rn.2d",
- [], NoItinerary> {
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
let Constraints = "$src = $Rd";
}
def 4h4s : NeonI_2VMisc<0b0, U, 0b00, opcode,
(outs VPR128:$Rd), (ins VPR64:$Rn),
asmop # "\t$Rd.4s, $Rn.4h",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 2s2d : NeonI_2VMisc<0b0, U, 0b01, opcode,
(outs VPR128:$Rd), (ins VPR64:$Rn),
asmop # "\t$Rd.2d, $Rn.2s",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 8h4s : NeonI_2VMisc<0b1, U, 0b00, opcode,
(outs VPR128:$Rd), (ins VPR128:$Rn),
asmop # "2\t$Rd.4s, $Rn.8h",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 4s2d : NeonI_2VMisc<0b1, U, 0b01, opcode,
(outs VPR128:$Rd), (ins VPR128:$Rn),
asmop # "2\t$Rd.2d, $Rn.4s",
- [], NoItinerary>;
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
}
defm FCVTL : NeonI_2VMisc_HS_Extend<"fcvtl", 0b0, 0b10111>;
asmop # "\t$Rd.4s, $Rn.4s",
[(set (ResTy4s VPR128:$Rd),
(ResTy4s (Neon_Op (OpTy4s VPR128:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 2d : NeonI_2VMisc<0b1, U, {Size, 0b1}, opcode,
(outs VPR128:$Rd), (ins VPR128:$Rn),
asmop # "\t$Rd.2d, $Rn.2d",
[(set (ResTy2d VPR128:$Rd),
(ResTy2d (Neon_Op (OpTy2d VPR128:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
(outs VPR64:$Rd), (ins VPR64:$Rn),
asmop # "\t$Rd.2s, $Rn.2s",
[(set (ResTy2s VPR64:$Rd),
(ResTy2s (Neon_Op (OpTy2s VPR64:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
}
multiclass NeonI_2VMisc_fp_to_int<string asmop, bit Size, bit U,
int_arm_neon_vrecpe>;
defm FRSQRTE : NeonI_2VMisc_fp_to_fp<"frsqrte", 0b1, 0b1, 0b11101,
int_arm_neon_vrsqrte>;
+let SchedRW = [WriteFPSqrt, ReadFPSqrt] in {
defm FSQRT : NeonI_2VMisc_fp_to_fp<"fsqrt", 0b1, 0b1, 0b11111, fsqrt>;
+}
multiclass NeonI_2VMisc_S_Conv<string asmop, bit Size, bit U,
bits<5> opcode, SDPatternOperator Neon_Op> {
asmop # "\t$Rd.4s, $Rn.4s",
[(set (v4i32 VPR128:$Rd),
(v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
(outs VPR64:$Rd), (ins VPR64:$Rn),
asmop # "\t$Rd.2s, $Rn.2s",
[(set (v2i32 VPR64:$Rd),
(v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
}
defm URECPE : NeonI_2VMisc_S_Conv<"urecpe", 0b1, 0b0, 0b11100,
[(set (v16i8 VPR128:$Rd),
(v16i8 (opnode (v16i8 VPR128:$src),
(v16i8 VPR128:$Rn))))],
- NoItinerary>{
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
let Constraints = "$src = $Rd";
let Predicates = [HasNEON, HasCrypto];
}
asmop # "\t$Rd.16b, $Rn.16b",
[(set (v16i8 VPR128:$Rd),
(v16i8 (opnode (v16i8 VPR128:$Rn))))],
- NoItinerary>;
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]>;
def AESMC : NeonI_Cryptoaes<0b00, 0b00110, "aesmc", int_arm_neon_aesmc>;
def AESIMC : NeonI_Cryptoaes<0b00, 0b00111, "aesimc", int_arm_neon_aesimc>;
[(set (v4i32 VPR128:$Rd),
(v4i32 (opnode (v4i32 VPR128:$src),
(v4i32 VPR128:$Rn))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
let Constraints = "$src = $Rd";
let Predicates = [HasNEON, HasCrypto];
}
: NeonI_Crypto_SHA<size, opcode,
(outs FPR32:$Rd), (ins FPR32:$Rn),
asmop # "\t$Rd, $Rn",
- [], NoItinerary> {
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU]> {
let Predicates = [HasNEON, HasCrypto];
let hasSideEffects = 0;
}
(v4i32 (opnode (v4i32 VPR128:$src),
(v4i32 VPR128:$Rn),
(v4i32 VPR128:$Rm))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU, ReadFPALU]> {
let Constraints = "$src = $Rd";
let Predicates = [HasNEON, HasCrypto];
}
(v4i32 (opnode (v4i32 FPR128:$src),
(v4i32 FPR128:$Rn),
(v4i32 VPR128:$Rm))))],
- NoItinerary> {
+ NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU, ReadFPALU]> {
let Constraints = "$src = $Rd";
let Predicates = [HasNEON, HasCrypto];
}
(outs FPR128:$Rd),
(ins FPR128:$src, FPR32:$Rn, VPR128:$Rm),
asmop # "\t$Rd, $Rn, $Rm.4s",
- [], NoItinerary> {
+ [], NoItinerary>,
+ Sched<[WriteFPALU, ReadFPALU, ReadFPALU, ReadFPALU]> {
let Constraints = "$src = $Rd";
let hasSideEffects = 0;
let Predicates = [HasNEON, HasCrypto];