- MachineInstr *MI = SU->getInstr();
- MachineOperand &MO = MI->getOperand(OperIdx);
- unsigned Reg = MO.getReg();
-
- LaneBitmask DefLaneMask;
- LaneBitmask KillLaneMask;
- if (TrackLaneMasks) {
- bool IsKill = MO.getSubReg() == 0 || MO.isUndef();
- DefLaneMask = getLaneMaskForMO(MO);
- // If we have a <read-undef> flag, none of the lane values comes from an
- // earlier instruction.
- KillLaneMask = IsKill ? ~0u : DefLaneMask;
-
- // Clear undef flag, we'll re-add it later once we know which subregister
- // Def is first.
- MO.setIsUndef(false);
- } else {
- DefLaneMask = ~0u;
- KillLaneMask = ~0u;
- }
-
- if (MO.isDead()) {
- assert(CurrentVRegUses.find(Reg) == CurrentVRegUses.end() &&
- "Dead defs should have no uses");
- } else {
- // Add data dependence to all uses we found so far.
- const TargetSubtargetInfo &ST = MF.getSubtarget();
- for (VReg2SUnitOperIdxMultiMap::iterator I = CurrentVRegUses.find(Reg),
- E = CurrentVRegUses.end(); I != E; /*empty*/) {
- LaneBitmask LaneMask = I->LaneMask;
- // Ignore uses of other lanes.
- if ((LaneMask & KillLaneMask) == 0) {
- ++I;
- continue;
- }
-
- if ((LaneMask & DefLaneMask) != 0) {
- SUnit *UseSU = I->SU;
- MachineInstr *Use = UseSU->getInstr();
- SDep Dep(SU, SDep::Data, Reg);
- Dep.setLatency(SchedModel.computeOperandLatency(MI, OperIdx, Use,
- I->OperandIndex));
- ST.adjustSchedDependency(SU, UseSU, Dep);
- UseSU->addPred(Dep);
- }
-
- LaneMask &= ~KillLaneMask;
- // If we found a Def for all lanes of this use, remove it from the list.
- if (LaneMask != 0) {
- I->LaneMask = LaneMask;
- ++I;
- } else
- I = CurrentVRegUses.erase(I);
- }
- }