+ pCRU_Reg->CRU_MODE_CON = (0x3<<((pll_id*4) + 16)) | (0x1<<(pll_id*4)); //PLL normal
+ dsb();
+ }
+ }
+ dsb();
+out:
+ return ret;
+}
+
+/*****************************************
+NR NO NF Fout freq Step finally use
+1 8 12.5 - 62.5 37.5MHz - 187.5MHz 3MHz 50MHz <= 150MHz
+1 6 12.5 - 62.5 50MHz - 250MHz 4MHz 150MHz <= 200MHz
+1 4 12.5 - 62.5 75MHz - 375MHz 6MHz 200MHz <= 300MHz
+1 2 12.5 - 62.5 150MHz - 750MHz 12MHz 300MHz <= 600MHz
+1 1 12.5 - 62.5 300MHz - 1500MHz 24MHz 600MHz <= 1200MHz
+******************************************/
+uint32_t __sramlocalfunc ddr_set_pll_rk3188_plus(uint32_t nMHz, uint32_t set)
+{
+ uint32_t ret = 0;
+ int delay = 1000;
+ uint32_t pll_id=1; //DPLL
+
+ if(nMHz == 24)
+ {
+ ret = 24;
+ goto out;
+ }
+
+ if(!set)
+ {
+ dpllvaluel = ddr_get_pll_freq(DPLL);
+ gpllvaluel = ddr_get_pll_freq(GPLL);
+
+ if(ddr_select_gpll_div > 0)
+ {
+ if(ddr_select_gpll_div == 4)
+ ret = gpllvaluel/4;
+ else if(ddr_select_gpll_div == 2)
+ ret = gpllvaluel/2;
+ else
+ ret=gpllvaluel;
+ }
+ else
+ {
+ if(nMHz <= 150)
+ {
+ clkod = 8;
+ }
+ else if(nMHz <= 200)
+ {
+ clkod = 6;
+ }
+ else if(nMHz <= 300)
+ {
+ clkod = 4;
+ }
+ else if(nMHz <= 600)
+ {
+ clkod = 2;
+ }
+ else
+ {
+ clkod = 1;
+ }
+ clkr = 1;
+ clkf=(nMHz*clkr*clkod)/24;
+ ret = (24*clkf)/(clkr*clkod);
+ }
+
+ }
+ else
+ {
+ if(ddr_select_gpll_div > 0)
+ {
+ if(ddr_select_gpll_div == 4)
+ {
+ pCRU_Reg->CRU_CLKGATE_CON[1] = 0x00800000;
+ pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
+ | (0x1<<8) //clk_ddr_src = G PLL
+ | 2; //clk_ddr_src:clk_ddrphy = 4:1
+ dsb();
+ }
+ if(ddr_select_gpll_div == 2)
+ {
+ pCRU_Reg->CRU_CLKGATE_CON[1] = 0x00800000;
+ pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
+ | (0x1<<8) //clk_ddr_src = G PLL
+ | 1; //clk_ddr_src:clk_ddrphy = 2:1
+ dsb();
+ }
+ else
+ {
+ pCRU_Reg->CRU_CLKGATE_CON[1] = 0x00800000;
+ pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
+ | (0x1<<8) //clk_ddr_src = G PLL
+ | 0; //clk_ddr_src:clk_ddrphy = 1:1
+ dsb();
+ }
+ }
+ else if((nMHz==dpllvaluel) && (set == 1))
+ {
+ // ddr_pll_clk: clk_ddr=1:1