usage: add i2s dts property "rockchip,xfer-mode"
rockchip,xfer-mode = <0>: i2s transfer mode.
rockchip,xfer-mode = <1>: pcm transfer mode.
if not define, use i2s transfer mode default.
pcm transfer mode is usually used for bt/modem voice.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
- reg: physical base address of the controller and length of memory mapped
region.
- i2s-id: i2s controller id,
- reg: physical base address of the controller and length of memory mapped
region.
- i2s-id: i2s controller id,
+- rockchip,xfer-mode: transfer mode select, 0:i2s, 1: pcm.
- clocks: must include clock specifiers corresponding to entries in the
clock-names property.
- clocks-names: list of clock names sorted in the same order as the clocks
- clocks: must include clock specifiers corresponding to entries in the
clock-names property.
- clocks-names: list of clock names sorted in the same order as the clocks
struct regmap *regmap;
bool tx_start;
bool rx_start;
struct regmap *regmap;
bool tx_start;
bool rx_start;
+ int xfer_mode; /* 0: i2s, 1: pcm */
#ifdef CLK_SET_LATER
struct delayed_work clk_delayed_work;
#endif
#ifdef CLK_SET_LATER
struct delayed_work clk_delayed_work;
#endif
goto err_unregister_component;
}
goto err_unregister_component;
}
+ ret = of_property_read_u32(node, "rockchip,xfer-mode", &i2s->xfer_mode);
+ if (ret < 0)
+ i2s->xfer_mode = I2S_XFER_MODE;
+
+ if (PCM_XFER_MODE == i2s->xfer_mode) {
+ regmap_update_bits(i2s->regmap, I2S_TXCR,
+ I2S_TXCR_TFS_MASK,
+ I2S_TXCR_TFS_PCM);
+ regmap_update_bits(i2s->regmap, I2S_RXCR,
+ I2S_RXCR_TFS_MASK,
+ I2S_RXCR_TFS_PCM);
+ }
+
rockchip_snd_txctrl(i2s, 0);
rockchip_snd_rxctrl(i2s, 0);
rockchip_snd_txctrl(i2s, 0);
rockchip_snd_rxctrl(i2s, 0);
return ret;
ret = regmap_reinit_cache(i2s->regmap, &rockchip_i2s_regmap_config);
return ret;
ret = regmap_reinit_cache(i2s->regmap, &rockchip_i2s_regmap_config);
+ if (PCM_XFER_MODE == i2s->xfer_mode) {
+ regmap_update_bits(i2s->regmap, I2S_TXCR,
+ I2S_TXCR_TFS_MASK,
+ I2S_TXCR_TFS_PCM);
+ regmap_update_bits(i2s->regmap, I2S_RXCR,
+ I2S_RXCR_TFS_MASK,
+ I2S_RXCR_TFS_PCM);
+ }
+
pm_runtime_put(dev);
dev_dbg(i2s->dev, "%s\n", __func__);
pm_runtime_put(dev);
dev_dbg(i2s->dev, "%s\n", __func__);
#define I2S_TXCR_TFS_SHIFT 5
#define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT)
#define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT)
#define I2S_TXCR_TFS_SHIFT 5
#define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT)
#define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT)
+#define I2S_TXCR_TFS_MASK (1 << I2S_TXCR_TFS_SHIFT)
#define I2S_TXCR_VDW_SHIFT 0
#define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT)
#define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT)
#define I2S_TXCR_VDW_SHIFT 0
#define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT)
#define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT)
#define I2S_RXCR_TFS_SHIFT 5
#define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT)
#define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT)
#define I2S_RXCR_TFS_SHIFT 5
#define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT)
#define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT)
+#define I2S_RXCR_TFS_MASK (1 << I2S_RXCR_TFS_SHIFT)
#define I2S_RXCR_VDW_SHIFT 0
#define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT)
#define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT)
#define I2S_RXCR_VDW_SHIFT 0
#define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT)
#define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT)
#define I2S_CHANNEL_4 4
#define I2S_CHANNEL_2 2
#define I2S_CHANNEL_4 4
#define I2S_CHANNEL_2 2
+#define I2S_XFER_MODE 0
+#define PCM_XFER_MODE 1
+
#endif /* __RK_I2S_H__ */
#endif /* __RK_I2S_H__ */