If the crtc pll status is not init, always cause mode_changed
at first dclk source generate, that would cause logo flush
fixup(
10a90aa drm/rockchip: support setting specail pll for hdmi)
Change-Id: I0ee20fd098654ff89f268be82b50d2d5b605e9d5
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
static void vop_crtc_reset(struct drm_crtc *crtc)
{
struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
static void vop_crtc_reset(struct drm_crtc *crtc)
{
struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
+ struct rockchip_drm_private *private = crtc->dev->dev_private;
+ struct vop *vop = to_vop(crtc);
if (crtc->state) {
__drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
if (crtc->state) {
__drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
return;
crtc->state = &s->base;
crtc->state->crtc = crtc;
return;
crtc->state = &s->base;
crtc->state->crtc = crtc;
+
+ if (vop->dclk_source) {
+ struct clk *parent;
+
+ parent = clk_get_parent(vop->dclk_source);
+ if (parent) {
+ if (clk_is_match(private->default_pll.pll, parent))
+ s->pll = &private->default_pll;
+ else if (clk_is_match(private->hdmi_pll.pll, parent))
+ s->pll = &private->hdmi_pll;
+ if (s->pll)
+ s->pll->use_count++;
+ }
+ }
s->left_margin = 100;
s->right_margin = 100;
s->top_margin = 100;
s->left_margin = 100;
s->right_margin = 100;
s->top_margin = 100;