- // 2i64 vector logical shifts can efficiently avoid scalarization - do the
- // shifts per-lane and then shuffle the partial results back together.
- if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
- // Splat the shift amounts so the scalar shifts above will catch it.
- SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
- SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
- SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
- SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
- return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
- }
-