Fix a bug where the x86 backend would reject 64-bit r constraints when

in 32-bit mode instead of assigning a register pair.  This has nothing to
do with PR2356, but I happened to notice it while working on it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57704 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index d32a9f052d4a9bbdbf0506f64cc610d095dcc476..0607797b713333009bb1953c2120ee0bb28b8f60 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -7511,7 +7511,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
     case 'l':   // INDEX_REGS
       if (VT == MVT::i64 && Subtarget->is64Bit())
         return std::make_pair(0U, X86::GR64RegisterClass);
     case 'l':   // INDEX_REGS
       if (VT == MVT::i64 && Subtarget->is64Bit())
         return std::make_pair(0U, X86::GR64RegisterClass);

-      if (VT == MVT::i32)
+      if (VT == MVT::i32 || VT == MVT::i64)

         return std::make_pair(0U, X86::GR32RegisterClass);
       else if (VT == MVT::i16)
         return std::make_pair(0U, X86::GR16RegisterClass);
         return std::make_pair(0U, X86::GR32RegisterClass);
       else if (VT == MVT::i16)
         return std::make_pair(0U, X86::GR16RegisterClass);

diff --git a/test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll b/test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll
new file mode 100644 (file)
index 0000000..eb2ec37
--- /dev/null
+++ b/test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll
@@ -0,0 +1,9 @@
+; RUN: llvm-as < %s | llc -march=x86
+; RUN: llvm-as < %s | llc -march=x86-64
+
+define void @test(i64 %x) nounwind {
+entry:
+       tail call void asm sideeffect "ASM: $0", "r,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind
+       ret void
+}
+