AVX-512: Fixed a bug in shufflevector lowering.

PALIGNR instruction does not exist in AVX-512F set.
Added a test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215526 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 96f01c8b245e94c874961fa6237c1dc6baa55592..98eedb8ec6ee70f8adc75e076f53fd473b93fcc5 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -3872,7 +3872,8 @@ static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
                           const X86Subtarget *Subtarget) {
   if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
                           const X86Subtarget *Subtarget) {
   if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||

-      (VT.is256BitVector() && !Subtarget->hasInt256()))
+      (VT.is256BitVector() && !Subtarget->hasInt256()) ||
+      VT.is512BitVector())

     // FIXME: Add AVX512BW.
     return false;
 
     // FIXME: Add AVX512BW.
     return false;
 

diff --git a/test/CodeGen/X86/avx512-shuffle.ll b/test/CodeGen/X86/avx512-shuffle.ll
index bae99d97b21a4f2ce6590448c9068f9db5ec1ee2..964971e6f6238caebc176873da4016c307a26fe8 100644 (file)
--- a/test/CodeGen/X86/avx512-shuffle.ll
+++ b/test/CodeGen/X86/avx512-shuffle.ll
@@ -199,6 +199,24 @@ define <16 x i32> @test15(<16 x i32> %a) {
  %b = shufflevector <16 x i32> %a, <16 x i32> undef, <16 x i32><i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
  ret <16 x i32> %b
 }
  %b = shufflevector <16 x i32> %a, <16 x i32> undef, <16 x i32><i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
  ret <16 x i32> %b
 }

+
+; CHECK-LABEL: valign_test_v16f32
+; CHECK: valignd $2, %zmm0, %zmm0
+; CHECK: ret
+define <16 x float> @valign_test_v16f32(<16 x float> %a, <16 x float> %b) nounwind {
+  %c = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32><i32 2, i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 undef, i32 10, i32 11, i32 undef, i32 undef, i32 14, i32 15, i32 undef, i32 undef>
+  ret <16 x float> %c
+}
+
+; CHECK-LABEL: valign_test_v16i32
+; CHECK: valignd $2, %zmm0, %zmm0
+; CHECK: ret
+define <16 x i32> @valign_test_v16i32(<16 x i32> %a, <16 x i32> %b) nounwind {
+  %c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32><i32 2, i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 undef, i32 10, i32 11, i32 undef, i32 undef, i32 14, i32 15, i32 undef, i32 undef>
+  ret <16 x i32> %c
+}
+
+

 ; CHECK-LABEL: test16
 ; CHECK: valignq $2, %zmm0, %zmm1
 ; CHECK: ret
 ; CHECK-LABEL: test16
 ; CHECK: valignq $2, %zmm0, %zmm1
 ; CHECK: ret