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[MIPS] Make csum_partial more readable
author
Atsushi Nemoto
<anemo@mba.ocn.ne.jp>
Thu, 7 Dec 2006 16:04:31 +0000
(
01:04
+0900)
committer
Ralf Baechle
<ralf@linux-mips.org>
Sat, 9 Dec 2006 01:03:59 +0000
(
01:03
+0000)
Use standard o32 register name instead of T0, T1, etc, like memcpy.S.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/lib/csum_partial.S
patch
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diff --git
a/arch/mips/lib/csum_partial.S
b/arch/mips/lib/csum_partial.S
index 15611d9df7ac6771d30be99e716f5ab2c60a21d4..3bffdbb1c1f90f2dc33f4b94ab7b622cabbd93f4 100644
(file)
--- a/
arch/mips/lib/csum_partial.S
+++ b/
arch/mips/lib/csum_partial.S
@@
-12,19
+12,23
@@
#include <asm/regdef.h>
#ifdef CONFIG_64BIT
#include <asm/regdef.h>
#ifdef CONFIG_64BIT
-#define T0 ta0
-#define T1 ta1
-#define T2 ta2
-#define T3 ta3
-#define T4 t0
-#define T7 t3
-#else
-#define T0 t0
-#define T1 t1
-#define T2 t2
-#define T3 t3
-#define T4 t4
-#define T7 t7
+/*
+ * As we are sharing code base with the mips32 tree (which use the o32 ABI
+ * register definitions). We need to redefine the register definitions from
+ * the n64 ABI register naming to the o32 ABI register naming.
+ */
+#undef t0
+#undef t1
+#undef t2
+#undef t3
+#define t0 $8
+#define t1 $9
+#define t2 $10
+#define t3 $11
+#define t4 $12
+#define t5 $13
+#define t6 $14
+#define t7 $15
#endif
#define ADDC(sum,reg) \
#endif
#define ADDC(sum,reg) \
@@
-64,37
+68,37
@@
/* unknown src alignment and < 8 bytes to go */
small_csumcpy:
/* unknown src alignment and < 8 bytes to go */
small_csumcpy:
- move a1,
T
2
+ move a1,
t
2
- andi
T
0, a1, 4
- beqz
T
0, 1f
- andi
T
0, a1, 2
+ andi
t
0, a1, 4
+ beqz
t
0, 1f
+ andi
t
0, a1, 2
/* Still a full word to go */
/* Still a full word to go */
- ulw
T
1, (src)
+ ulw
t
1, (src)
PTR_ADDIU src, 4
PTR_ADDIU src, 4
- ADDC(sum,
T
1)
+ ADDC(sum,
t
1)
-1: move
T
1, zero
- beqz
T
0, 1f
- andi
T
0, a1, 1
+1: move
t
1, zero
+ beqz
t
0, 1f
+ andi
t
0, a1, 1
/* Still a halfword to go */
/* Still a halfword to go */
- ulhu
T
1, (src)
+ ulhu
t
1, (src)
PTR_ADDIU src, 2
PTR_ADDIU src, 2
-1: beqz
T
0, 1f
- sll
T1, T
1, 16
+1: beqz
t
0, 1f
+ sll
t1, t
1, 16
- lbu
T
2, (src)
+ lbu
t
2, (src)
nop
#ifdef __MIPSEB__
nop
#ifdef __MIPSEB__
- sll
T2, T
2, 8
+ sll
t2, t
2, 8
#endif
#endif
- or
T1, T
2
+ or
t1, t
2
-1: ADDC(sum,
T
1)
+1: ADDC(sum,
t
1)
/* fold checksum */
sll v1, sum, 16
/* fold checksum */
sll v1, sum, 16
@@
-104,7
+108,7
@@
small_csumcpy:
addu sum, v1
/* odd buffer alignment? */
addu sum, v1
/* odd buffer alignment? */
- beqz
T
7, 1f
+ beqz
t
7, 1f
nop
sll v1, sum, 8
srl sum, sum, 8
nop
sll v1, sum, 8
srl sum, sum, 8
@@
-122,25
+126,25
@@
small_csumcpy:
.align 5
LEAF(csum_partial)
move sum, zero
.align 5
LEAF(csum_partial)
move sum, zero
- move
T
7, zero
+ move
t
7, zero
sltiu t8, a1, 0x8
bnez t8, small_csumcpy /* < 8 bytes to copy */
sltiu t8, a1, 0x8
bnez t8, small_csumcpy /* < 8 bytes to copy */
- move
T
2, a1
+ move
t
2, a1
beqz a1, out
beqz a1, out
- andi
T
7, src, 0x1 /* odd buffer? */
+ andi
t
7, src, 0x1 /* odd buffer? */
hword_align:
hword_align:
- beqz
T
7, word_align
+ beqz
t
7, word_align
andi t8, src, 0x2
andi t8, src, 0x2
- lbu
T
0, (src)
+ lbu
t
0, (src)
LONG_SUBU a1, a1, 0x1
#ifdef __MIPSEL__
LONG_SUBU a1, a1, 0x1
#ifdef __MIPSEL__
- sll
T0, T
0, 8
+ sll
t0, t
0, 8
#endif
#endif
- ADDC(sum,
T
0)
+ ADDC(sum,
t
0)
PTR_ADDU src, src, 0x1
andi t8, src, 0x2
PTR_ADDU src, src, 0x1
andi t8, src, 0x2
@@
-148,9
+152,9
@@
word_align:
beqz t8, dword_align
sltiu t8, a1, 56
beqz t8, dword_align
sltiu t8, a1, 56
- lhu
T
0, (src)
+ lhu
t
0, (src)
LONG_SUBU a1, a1, 0x2
LONG_SUBU a1, a1, 0x2
- ADDC(sum,
T
0)
+ ADDC(sum,
t
0)
sltiu t8, a1, 56
PTR_ADDU src, src, 0x2
sltiu t8, a1, 56
PTR_ADDU src, src, 0x2
@@
-162,9
+166,9
@@
dword_align:
beqz t8, qword_align
andi t8, src, 0x8
beqz t8, qword_align
andi t8, src, 0x8
- lw
T
0, 0x00(src)
+ lw
t
0, 0x00(src)
LONG_SUBU a1, a1, 0x4
LONG_SUBU a1, a1, 0x4
- ADDC(sum,
T
0)
+ ADDC(sum,
t
0)
PTR_ADDU src, src, 0x4
andi t8, src, 0x8
PTR_ADDU src, src, 0x4
andi t8, src, 0x8
@@
-172,11
+176,11
@@
qword_align:
beqz t8, oword_align
andi t8, src, 0x10
beqz t8, oword_align
andi t8, src, 0x10
- lw
T
0, 0x00(src)
- lw
T
1, 0x04(src)
+ lw
t
0, 0x00(src)
+ lw
t
1, 0x04(src)
LONG_SUBU a1, a1, 0x8
LONG_SUBU a1, a1, 0x8
- ADDC(sum,
T
0)
- ADDC(sum,
T
1)
+ ADDC(sum,
t
0)
+ ADDC(sum,
t
1)
PTR_ADDU src, src, 0x8
andi t8, src, 0x10
PTR_ADDU src, src, 0x8
andi t8, src, 0x10
@@
-184,46
+188,46
@@
oword_align:
beqz t8, begin_movement
LONG_SRL t8, a1, 0x7
beqz t8, begin_movement
LONG_SRL t8, a1, 0x7
- lw
T
3, 0x08(src)
- lw
T
4, 0x0c(src)
- lw
T
0, 0x00(src)
- lw
T
1, 0x04(src)
- ADDC(sum,
T
3)
- ADDC(sum,
T
4)
- ADDC(sum,
T
0)
- ADDC(sum,
T
1)
+ lw
t
3, 0x08(src)
+ lw
t
4, 0x0c(src)
+ lw
t
0, 0x00(src)
+ lw
t
1, 0x04(src)
+ ADDC(sum,
t
3)
+ ADDC(sum,
t
4)
+ ADDC(sum,
t
0)
+ ADDC(sum,
t
1)
LONG_SUBU a1, a1, 0x10
PTR_ADDU src, src, 0x10
LONG_SRL t8, a1, 0x7
begin_movement:
beqz t8, 1f
LONG_SUBU a1, a1, 0x10
PTR_ADDU src, src, 0x10
LONG_SRL t8, a1, 0x7
begin_movement:
beqz t8, 1f
- andi
T
2, a1, 0x40
+ andi
t
2, a1, 0x40
move_128bytes:
move_128bytes:
- CSUM_BIGCHUNK(src, 0x00, sum,
T0, T1, T3, T
4)
- CSUM_BIGCHUNK(src, 0x20, sum,
T0, T1, T3, T
4)
- CSUM_BIGCHUNK(src, 0x40, sum,
T0, T1, T3, T
4)
- CSUM_BIGCHUNK(src, 0x60, sum,
T0, T1, T3, T
4)
+ CSUM_BIGCHUNK(src, 0x00, sum,
t0, t1, t3, t
4)
+ CSUM_BIGCHUNK(src, 0x20, sum,
t0, t1, t3, t
4)
+ CSUM_BIGCHUNK(src, 0x40, sum,
t0, t1, t3, t
4)
+ CSUM_BIGCHUNK(src, 0x60, sum,
t0, t1, t3, t
4)
LONG_SUBU t8, t8, 0x01
bnez t8, move_128bytes
PTR_ADDU src, src, 0x80
1:
LONG_SUBU t8, t8, 0x01
bnez t8, move_128bytes
PTR_ADDU src, src, 0x80
1:
- beqz
T
2, 1f
- andi
T
2, a1, 0x20
+ beqz
t
2, 1f
+ andi
t
2, a1, 0x20
move_64bytes:
move_64bytes:
- CSUM_BIGCHUNK(src, 0x00, sum,
T0, T1, T3, T
4)
- CSUM_BIGCHUNK(src, 0x20, sum,
T0, T1, T3, T
4)
+ CSUM_BIGCHUNK(src, 0x00, sum,
t0, t1, t3, t
4)
+ CSUM_BIGCHUNK(src, 0x20, sum,
t0, t1, t3, t
4)
PTR_ADDU src, src, 0x40
1:
PTR_ADDU src, src, 0x40
1:
- beqz
T
2, do_end_words
+ beqz
t
2, do_end_words
andi t8, a1, 0x1c
move_32bytes:
andi t8, a1, 0x1c
move_32bytes:
- CSUM_BIGCHUNK(src, 0x00, sum,
T0, T1, T3, T
4)
+ CSUM_BIGCHUNK(src, 0x00, sum,
t0, t1, t3, t
4)
andi t8, a1, 0x1c
PTR_ADDU src, src, 0x20
andi t8, a1, 0x1c
PTR_ADDU src, src, 0x20
@@
-232,22
+236,22
@@
do_end_words:
LONG_SRL t8, t8, 0x2
end_words:
LONG_SRL t8, t8, 0x2
end_words:
- lw
T
0, (src)
+ lw
t
0, (src)
LONG_SUBU t8, t8, 0x1
LONG_SUBU t8, t8, 0x1
- ADDC(sum,
T
0)
+ ADDC(sum,
t
0)
bnez t8, end_words
PTR_ADDU src, src, 0x4
maybe_end_cruft:
bnez t8, end_words
PTR_ADDU src, src, 0x4
maybe_end_cruft:
- andi
T
2, a1, 0x3
+ andi
t
2, a1, 0x3
small_memcpy:
small_memcpy:
- j small_csumcpy; move a1,
T
2 /* XXX ??? */
+ j small_csumcpy; move a1,
t
2 /* XXX ??? */
beqz t2, out
beqz t2, out
- move a1,
T
2
+ move a1,
t
2
end_bytes:
end_bytes:
- lb
T
0, (src)
+ lb
t
0, (src)
LONG_SUBU a1, a1, 0x1
bnez a2, end_bytes
PTR_ADDU src, src, 0x1
LONG_SUBU a1, a1, 0x1
bnez a2, end_bytes
PTR_ADDU src, src, 0x1