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Remove the NEON N2VSInt instruction class: it's only used in one place and
author
Bob Wilson
<bob.wilson@apple.com>
Wed, 17 Feb 2010 22:42:54 +0000
(22:42 +0000)
committer
Bob Wilson
<bob.wilson@apple.com>
Wed, 17 Feb 2010 22:42:54 +0000
(22:42 +0000)
since it has no pattern, there's not much point in distinguishing an "N2VS"
class for intrinsics anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96525
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/ARM/ARMInstrNEON.td
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diff --git
a/lib/Target/ARM/ARMInstrNEON.td
b/lib/Target/ARM/ARMInstrNEON.td
index 6d7f242127c0d35a0a9f009abb13e5913e231ecb..f981572c76c9adb4f13bb1f3b97ab5eeb7a47ac8 100644
(file)
--- a/
lib/Target/ARM/ARMInstrNEON.td
+++ b/
lib/Target/ARM/ARMInstrNEON.td
@@
-586,14
+586,7
@@
class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
(ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src", "",
[(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
(ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src", "",
[(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
-// Basic 2-register intrinsics: single-, double- and quad-register.
-class N2VSInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
- bits<2> op17_16, bits<5> op11_7, bit op4,
- InstrItinClass itin, string OpcodeStr, string Dt,
- ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
- : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
- (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), itin,
- OpcodeStr, Dt, "$dst, $src", "", []>;
+// Basic 2-register intrinsics, both double- and quad-register.
class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
bits<2> op17_16, bits<5> op11_7, bit op4,
InstrItinClass itin, string OpcodeStr, string Dt,
class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
bits<2> op17_16, bits<5> op11_7, bit op4,
InstrItinClass itin, string OpcodeStr, string Dt,
@@
-3018,8
+3011,9
@@
def : N3VSPat<fmul, VMULfd_sfp>;
// Vector Absolute used for single-precision FP
let neverHasSideEffects = 1 in
// Vector Absolute used for single-precision FP
let neverHasSideEffects = 1 in
-def VABSfd_sfp : N2VSInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, IIC_VUNAD,
- "vabs", "f32", v2f32, v2f32, int_arm_neon_vabs>;
+def VABSfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 0,
+ (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
+ "vabs", "f32", "$dst, $src", "", []>;
def : N2VSPat<fabs, f32, v2f32, VABSfd_sfp>;
// Vector Negate used for single-precision FP
def : N2VSPat<fabs, f32, v2f32, VABSfd_sfp>;
// Vector Negate used for single-precision FP