- // Bitvector table is NumRCs x NumSubIndexes x BVWords, where BVWords is
- // the number of 32-bit words required to represent all register classes.
- const unsigned BVWords = (RegisterClasses.size()+31)/32;
- BitVector BV(RegisterClasses.size());
-
- // Emit super-register class tables. For each register class, RC, create a
- // list of subreg indices and bit masks, (Idx, Mask). The bit mask has a
- // bit for every superreg regclass, SuperRC, that satisfies:
- //
- // For all SuperReg in SuperRC: SuperReg:Idx in RC
- //
- // The 0-terminated list of subreg indices starts at:
- //
- // SuperRegIdxSeqs + SuperRegIdxOffset[RC]
- //
- // The corresponding bitmasks start at:
- //
- // SuperRegMasks + SuperRegMaskOffset[RC]
- //
- // Every bit mask present in the list has at least one bit set.
-
- // Compress the sub-reg index lists.
- SmallVector<std::vector<const CodeGenSubRegIndex*>, 8>
- SRILists(RegisterClasses.size());
- SequenceToOffsetTable<std::vector<const CodeGenSubRegIndex*> > SRISeqs;
-
- // Emit the SuperRegMasks table while computing per-RC offsets.
- SmallVector<unsigned, 8> MaskOffsets;
- unsigned MaskOffset = 0;
- OS << "static const uint32_t SuperRegMasks[][" << BVWords << "] = {\n";
- for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
- const CodeGenRegisterClass &RC = *RegisterClasses[rci];
- OS << " // " << RC.getName() << '\n';
- MaskOffsets.push_back(MaskOffset);
- std::vector<const CodeGenSubRegIndex*> &SRIList = SRILists[rci];
- for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
- CodeGenSubRegIndex *Idx = SubRegIndices[sri];
- BV.reset();
- RC.getSuperRegClasses(Idx, BV);
- if (BV.none())
- continue;
- SRIList.push_back(Idx);
- OS << " { ";
- printBitVectorAsHex(OS, BV, 32);
- OS << "},\t// " << Idx->getName() << '\n';
- ++MaskOffset;
- }
- SRISeqs.add(SRIList);
- }
- OS << "};\n\nstatic const unsigned SuperRegMaskOffset[] = {\n ";
- for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci)
- OS << ' ' << MaskOffsets[rci] << ',';
- OS << "\n};\n\nstatic const uint16_t SuperRegIdxSeqs[] = {\n";
- SRISeqs.layout();
- SRISeqs.emit(OS, printSubRegIndex);
- OS << "};\n\nstatic const unsigned SuperRegIdxOffset[] = {\n ";
- for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci)
- OS << ' ' << SRISeqs.get(SRILists[rci]) << ',';
- OS << "\n};\n\n";
-