We need more control over the ordering of dpm init with
respect to the rest of the asic. Specifically, the SMC
has to be initialized before the rlc and cg/pg. The pm
code currently initializes late in the driver, but we need
it to happen much earlier so move pm handling into the asic
specific callbacks.
This makes dpm more reliable and makes clockgating work
properly on CIK parts and should help on SI parts as well.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
21 files changed:
struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
+extern int ni_mc_load_microcode(struct radeon_device *rdev);
//********* BARTS **************//
static const u32 barts_cgcg_cgls_default[] =
//********* BARTS **************//
static const u32 barts_cgcg_cgls_default[] =
void btc_dpm_setup_asic(struct radeon_device *rdev)
{
struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
void btc_dpm_setup_asic(struct radeon_device *rdev)
{
struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
+ r = ni_mc_load_microcode(rdev);
+ if (r)
+ DRM_ERROR("Failed to load MC firmware!\n");
rv770_get_memory_type(rdev);
rv740_read_clock_registers(rdev);
btc_read_arb_registers(rdev);
rv770_get_memory_type(rdev);
rv740_read_clock_registers(rdev);
btc_read_arb_registers(rdev);
struct atom_voltage_table *voltage_table);
extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
struct atom_voltage_table *voltage_table);
extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
+extern int ci_mc_load_microcode(struct radeon_device *rdev);
static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
struct atom_voltage_table_entry *voltage_table,
static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
struct atom_voltage_table_entry *voltage_table,
void ci_dpm_setup_asic(struct radeon_device *rdev)
{
void ci_dpm_setup_asic(struct radeon_device *rdev)
{
+ int r;
+
+ r = ci_mc_load_microcode(rdev);
+ if (r)
+ DRM_ERROR("Failed to load MC firmware!\n");
ci_read_clock_registers(rdev);
ci_get_memory_type(rdev);
ci_enable_acpi_power_management(rdev);
ci_read_clock_registers(rdev);
ci_get_memory_type(rdev);
ci_enable_acpi_power_management(rdev);
* Load the GDDR MC ucode into the hw (CIK).
* Returns 0 on success, error on failure.
*/
* Load the GDDR MC ucode into the hw (CIK).
* Returns 0 on success, error on failure.
*/
-static int ci_mc_load_microcode(struct radeon_device *rdev)
+int ci_mc_load_microcode(struct radeon_device *rdev)
{
const __be32 *fw_data;
u32 running, blackout = 0;
{
const __be32 *fw_data;
u32 running, blackout = 0;
- if (!(rdev->flags & RADEON_IS_IGP)) {
+ if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) {
r = ci_mc_load_microcode(rdev);
if (r) {
DRM_ERROR("Failed to load MC firmware!\n");
r = ci_mc_load_microcode(rdev);
if (r) {
DRM_ERROR("Failed to load MC firmware!\n");
/* init golden registers */
cik_init_golden_registers(rdev);
/* init golden registers */
cik_init_golden_registers(rdev);
+ radeon_pm_resume(rdev);
+
rdev->accel_working = true;
r = cik_startup(rdev);
if (r) {
rdev->accel_working = true;
r = cik_startup(rdev);
if (r) {
*/
int cik_suspend(struct radeon_device *rdev)
{
*/
int cik_suspend(struct radeon_device *rdev)
{
+ radeon_pm_suspend(rdev);
dce6_audio_fini(rdev);
radeon_vm_manager_fini(rdev);
cik_cp_enable(rdev, false);
dce6_audio_fini(rdev);
radeon_vm_manager_fini(rdev);
cik_cp_enable(rdev, false);
+ /* Initialize power management */
+ radeon_pm_init(rdev);
+
ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
ring->ring_obj = NULL;
r600_ring_init(rdev, ring, 1024 * 1024);
ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
ring->ring_obj = NULL;
r600_ring_init(rdev, ring, 1024 * 1024);
*/
void cik_fini(struct radeon_device *rdev)
{
*/
void cik_fini(struct radeon_device *rdev)
{
cik_cp_fini(rdev);
cik_sdma_fini(rdev);
cik_fini_pg(rdev);
cik_cp_fini(rdev);
cik_sdma_fini(rdev);
cik_fini_pg(rdev);
evergreen_mc_program(rdev);
evergreen_mc_program(rdev);
- if (ASIC_IS_DCE5(rdev)) {
+ if (ASIC_IS_DCE5(rdev) && !rdev->pm.dpm_enabled) {
r = ni_mc_load_microcode(rdev);
if (r) {
DRM_ERROR("Failed to load MC firmware!\n");
r = ni_mc_load_microcode(rdev);
if (r) {
DRM_ERROR("Failed to load MC firmware!\n");
/* init golden registers */
evergreen_init_golden_registers(rdev);
/* init golden registers */
evergreen_init_golden_registers(rdev);
+ radeon_pm_resume(rdev);
+
rdev->accel_working = true;
r = evergreen_startup(rdev);
if (r) {
rdev->accel_working = true;
r = evergreen_startup(rdev);
if (r) {
int evergreen_suspend(struct radeon_device *rdev)
{
int evergreen_suspend(struct radeon_device *rdev)
{
+ radeon_pm_suspend(rdev);
r600_audio_fini(rdev);
uvd_v1_0_fini(rdev);
radeon_uvd_suspend(rdev);
r600_audio_fini(rdev);
uvd_v1_0_fini(rdev);
radeon_uvd_suspend(rdev);
+ /* Initialize power management */
+ radeon_pm_init(rdev);
+
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
void evergreen_fini(struct radeon_device *rdev)
{
void evergreen_fini(struct radeon_device *rdev)
{
r600_audio_fini(rdev);
r700_cp_fini(rdev);
r600_dma_fini(rdev);
r600_audio_fini(rdev);
r700_cp_fini(rdev);
r600_dma_fini(rdev);
evergreen_mc_program(rdev);
evergreen_mc_program(rdev);
- if (!(rdev->flags & RADEON_IS_IGP)) {
+ if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) {
r = ni_mc_load_microcode(rdev);
if (r) {
DRM_ERROR("Failed to load MC firmware!\n");
r = ni_mc_load_microcode(rdev);
if (r) {
DRM_ERROR("Failed to load MC firmware!\n");
/* init golden registers */
ni_init_golden_registers(rdev);
/* init golden registers */
ni_init_golden_registers(rdev);
+ radeon_pm_resume(rdev);
+
rdev->accel_working = true;
r = cayman_startup(rdev);
if (r) {
rdev->accel_working = true;
r = cayman_startup(rdev);
if (r) {
int cayman_suspend(struct radeon_device *rdev)
{
int cayman_suspend(struct radeon_device *rdev)
{
+ radeon_pm_suspend(rdev);
if (ASIC_IS_DCE6(rdev))
dce6_audio_fini(rdev);
else
if (ASIC_IS_DCE6(rdev))
dce6_audio_fini(rdev);
else
+ /* Initialize power management */
+ radeon_pm_init(rdev);
+
ring->ring_obj = NULL;
r600_ring_init(rdev, ring, 1024 * 1024);
ring->ring_obj = NULL;
r600_ring_init(rdev, ring, 1024 * 1024);
void cayman_fini(struct radeon_device *rdev)
{
void cayman_fini(struct radeon_device *rdev)
{
cayman_cp_fini(rdev);
cayman_dma_fini(rdev);
r600_irq_fini(rdev);
cayman_cp_fini(rdev);
cayman_dma_fini(rdev);
r600_irq_fini(rdev);
struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
+extern int ni_mc_load_microcode(struct radeon_device *rdev);
+
struct ni_power_info *ni_get_pi(struct radeon_device *rdev)
{
struct ni_power_info *pi = rdev->pm.dpm.priv;
struct ni_power_info *ni_get_pi(struct radeon_device *rdev)
{
struct ni_power_info *pi = rdev->pm.dpm.priv;
void ni_dpm_setup_asic(struct radeon_device *rdev)
{
struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
void ni_dpm_setup_asic(struct radeon_device *rdev)
{
struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
+ r = ni_mc_load_microcode(rdev);
+ if (r)
+ DRM_ERROR("Failed to load MC firmware!\n");
ni_read_clock_registers(rdev);
btc_read_arb_registers(rdev);
rv770_get_memory_type(rdev);
ni_read_clock_registers(rdev);
btc_read_arb_registers(rdev);
rv770_get_memory_type(rdev);
/* Initialize surface registers */
radeon_surface_init(rdev);
/* Initialize surface registers */
radeon_surface_init(rdev);
+ radeon_pm_resume(rdev);
+
rdev->accel_working = true;
r = r100_startup(rdev);
if (r) {
rdev->accel_working = true;
r = r100_startup(rdev);
if (r) {
int r100_suspend(struct radeon_device *rdev)
{
int r100_suspend(struct radeon_device *rdev)
{
+ radeon_pm_suspend(rdev);
r100_cp_disable(rdev);
radeon_wb_disable(rdev);
r100_irq_disable(rdev);
r100_cp_disable(rdev);
radeon_wb_disable(rdev);
r100_irq_disable(rdev);
void r100_fini(struct radeon_device *rdev)
{
void r100_fini(struct radeon_device *rdev)
{
r100_cp_fini(rdev);
radeon_wb_fini(rdev);
radeon_ib_pool_fini(rdev);
r100_cp_fini(rdev);
radeon_wb_fini(rdev);
radeon_ib_pool_fini(rdev);
}
r100_set_safe_registers(rdev);
}
r100_set_safe_registers(rdev);
+ /* Initialize power management */
+ radeon_pm_init(rdev);
+
rdev->accel_working = true;
r = r100_startup(rdev);
if (r) {
rdev->accel_working = true;
r = r100_startup(rdev);
if (r) {
/* Initialize surface registers */
radeon_surface_init(rdev);
/* Initialize surface registers */
radeon_surface_init(rdev);
+ radeon_pm_resume(rdev);
+
rdev->accel_working = true;
r = r300_startup(rdev);
if (r) {
rdev->accel_working = true;
r = r300_startup(rdev);
if (r) {
int r300_suspend(struct radeon_device *rdev)
{
int r300_suspend(struct radeon_device *rdev)
{
+ radeon_pm_suspend(rdev);
r100_cp_disable(rdev);
radeon_wb_disable(rdev);
r100_irq_disable(rdev);
r100_cp_disable(rdev);
radeon_wb_disable(rdev);
r100_irq_disable(rdev);
void r300_fini(struct radeon_device *rdev)
{
void r300_fini(struct radeon_device *rdev)
{
r100_cp_fini(rdev);
radeon_wb_fini(rdev);
radeon_ib_pool_fini(rdev);
r100_cp_fini(rdev);
radeon_wb_fini(rdev);
radeon_ib_pool_fini(rdev);
}
r300_set_reg_safe(rdev);
}
r300_set_reg_safe(rdev);
+ /* Initialize power management */
+ radeon_pm_init(rdev);
+
rdev->accel_working = true;
r = r300_startup(rdev);
if (r) {
rdev->accel_working = true;
r = r300_startup(rdev);
if (r) {
/* Initialize surface registers */
radeon_surface_init(rdev);
/* Initialize surface registers */
radeon_surface_init(rdev);
+ radeon_pm_resume(rdev);
+
rdev->accel_working = true;
r = r420_startup(rdev);
if (r) {
rdev->accel_working = true;
r = r420_startup(rdev);
if (r) {
int r420_suspend(struct radeon_device *rdev)
{
int r420_suspend(struct radeon_device *rdev)
{
+ radeon_pm_suspend(rdev);
r420_cp_errata_fini(rdev);
r100_cp_disable(rdev);
radeon_wb_disable(rdev);
r420_cp_errata_fini(rdev);
r100_cp_disable(rdev);
radeon_wb_disable(rdev);
void r420_fini(struct radeon_device *rdev)
{
void r420_fini(struct radeon_device *rdev)
{
r100_cp_fini(rdev);
radeon_wb_fini(rdev);
radeon_ib_pool_fini(rdev);
r100_cp_fini(rdev);
radeon_wb_fini(rdev);
radeon_ib_pool_fini(rdev);
}
r420_set_reg_safe(rdev);
}
r420_set_reg_safe(rdev);
+ /* Initialize power management */
+ radeon_pm_init(rdev);
+
rdev->accel_working = true;
r = r420_startup(rdev);
if (r) {
rdev->accel_working = true;
r = r420_startup(rdev);
if (r) {
/* Initialize surface registers */
radeon_surface_init(rdev);
/* Initialize surface registers */
radeon_surface_init(rdev);
+ radeon_pm_resume(rdev);
+
rdev->accel_working = true;
r = r520_startup(rdev);
if (r) {
rdev->accel_working = true;
r = r520_startup(rdev);
if (r) {
return r;
rv515_set_safe_registers(rdev);
return r;
rv515_set_safe_registers(rdev);
+ /* Initialize power management */
+ radeon_pm_init(rdev);
+
rdev->accel_working = true;
r = r520_startup(rdev);
if (r) {
rdev->accel_working = true;
r = r520_startup(rdev);
if (r) {
/* post card */
atom_asic_init(rdev->mode_info.atom_context);
/* post card */
atom_asic_init(rdev->mode_info.atom_context);
+ radeon_pm_resume(rdev);
+
rdev->accel_working = true;
r = r600_startup(rdev);
if (r) {
rdev->accel_working = true;
r = r600_startup(rdev);
if (r) {
int r600_suspend(struct radeon_device *rdev)
{
int r600_suspend(struct radeon_device *rdev)
{
+ radeon_pm_suspend(rdev);
r600_audio_fini(rdev);
r600_cp_stop(rdev);
r600_dma_stop(rdev);
r600_audio_fini(rdev);
r600_cp_stop(rdev);
r600_dma_stop(rdev);
+ /* Initialize power management */
+ radeon_pm_init(rdev);
+
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
void r600_fini(struct radeon_device *rdev)
{
void r600_fini(struct radeon_device *rdev)
{
r600_audio_fini(rdev);
r600_cp_fini(rdev);
r600_dma_fini(rdev);
r600_audio_fini(rdev);
r600_cp_fini(rdev);
r600_dma_fini(rdev);
if ((radeon_testing & 1)) {
if (rdev->accel_working)
radeon_test_moves(rdev);
if ((radeon_testing & 1)) {
if (rdev->accel_working)
radeon_test_moves(rdev);
radeon_save_bios_scratch_regs(rdev);
radeon_save_bios_scratch_regs(rdev);
- radeon_pm_suspend(rdev);
radeon_suspend(rdev);
radeon_hpd_fini(rdev);
/* evict remaining vram memory */
radeon_suspend(rdev);
radeon_hpd_fini(rdev);
/* evict remaining vram memory */
if (r)
DRM_ERROR("ib ring test failed (%d).\n", r);
if (r)
DRM_ERROR("ib ring test failed (%d).\n", r);
- radeon_pm_resume(rdev);
+ if (rdev->pm.dpm_enabled) {
+ /* do dpm late init */
+ r = radeon_pm_late_init(rdev);
+ if (r) {
+ rdev->pm.dpm_enabled = false;
+ DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
+ }
+ }
+
radeon_restore_bios_scratch_regs(rdev);
if (fbcon) {
radeon_fbdev_set_suspend(rdev, 0);
console_unlock();
}
radeon_restore_bios_scratch_regs(rdev);
if (fbcon) {
radeon_fbdev_set_suspend(rdev, 0);
console_unlock();
}
/* init dig PHYs, disp eng pll */
if (rdev->is_atom_bios) {
radeon_atom_encoder_init(rdev);
/* init dig PHYs, disp eng pll */
if (rdev->is_atom_bios) {
radeon_atom_encoder_init(rdev);
/* setup afmt */
radeon_afmt_init(rdev);
/* setup afmt */
radeon_afmt_init(rdev);
- /* Initialize power management */
- radeon_pm_init(rdev);
-
radeon_fbdev_init(rdev);
drm_kms_helper_poll_init(rdev->ddev);
radeon_fbdev_init(rdev);
drm_kms_helper_poll_init(rdev->ddev);
+ if (rdev->pm.dpm_enabled) {
+ /* do dpm late init */
+ ret = radeon_pm_late_init(rdev);
+ if (ret) {
+ rdev->pm.dpm_enabled = false;
+ DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
+ }
+ /* set the dpm state for PX since there won't be
+ * a modeset to call this.
+ */
+ radeon_pm_compute_clocks(rdev);
+ }
+
{
radeon_fbdev_fini(rdev);
kfree(rdev->mode_info.bios_hardcoded_edid);
{
radeon_fbdev_fini(rdev);
kfree(rdev->mode_info.bios_hardcoded_edid);
if (rdev->mode_info.mode_config_initialized) {
radeon_afmt_fini(rdev);
if (rdev->mode_info.mode_config_initialized) {
radeon_afmt_fini(rdev);
mutex_unlock(&rdev->pm.mutex);
if (ret)
goto dpm_resume_fail;
mutex_unlock(&rdev->pm.mutex);
if (ret)
goto dpm_resume_fail;
- ret = radeon_pm_late_init(rdev);
- if (ret)
- goto dpm_resume_fail;
-
rdev->pm.dpm_enabled = true;
radeon_pm_compute_clocks(rdev);
return;
rdev->pm.dpm_enabled = true;
radeon_pm_compute_clocks(rdev);
return;
radeon_dpm_setup_asic(rdev);
ret = radeon_dpm_enable(rdev);
mutex_unlock(&rdev->pm.mutex);
radeon_dpm_setup_asic(rdev);
ret = radeon_dpm_enable(rdev);
mutex_unlock(&rdev->pm.mutex);
- if (ret)
- goto dpm_failed;
- ret = radeon_pm_late_init(rdev);
if (ret)
goto dpm_failed;
rdev->pm.dpm_enabled = true;
if (ret)
goto dpm_failed;
rdev->pm.dpm_enabled = true;
- radeon_pm_compute_clocks(rdev);
ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
if (ret)
ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
if (ret)
struct drm_crtc *crtc;
struct radeon_crtc *radeon_crtc;
struct drm_crtc *crtc;
struct radeon_crtc *radeon_crtc;
+ if (!rdev->pm.dpm_enabled)
+ return;
+
mutex_lock(&rdev->pm.mutex);
/* update active crtc counts */
mutex_lock(&rdev->pm.mutex);
/* update active crtc counts */
/* Initialize surface registers */
radeon_surface_init(rdev);
/* Initialize surface registers */
radeon_surface_init(rdev);
+ radeon_pm_resume(rdev);
+
rdev->accel_working = true;
r = rs400_startup(rdev);
if (r) {
rdev->accel_working = true;
r = rs400_startup(rdev);
if (r) {
int rs400_suspend(struct radeon_device *rdev)
{
int rs400_suspend(struct radeon_device *rdev)
{
+ radeon_pm_suspend(rdev);
r100_cp_disable(rdev);
radeon_wb_disable(rdev);
r100_irq_disable(rdev);
r100_cp_disable(rdev);
radeon_wb_disable(rdev);
r100_irq_disable(rdev);
void rs400_fini(struct radeon_device *rdev)
{
void rs400_fini(struct radeon_device *rdev)
{
r100_cp_fini(rdev);
radeon_wb_fini(rdev);
radeon_ib_pool_fini(rdev);
r100_cp_fini(rdev);
radeon_wb_fini(rdev);
radeon_ib_pool_fini(rdev);
return r;
r300_set_reg_safe(rdev);
return r;
r300_set_reg_safe(rdev);
+ /* Initialize power management */
+ radeon_pm_init(rdev);
+
rdev->accel_working = true;
r = rs400_startup(rdev);
if (r) {
rdev->accel_working = true;
r = rs400_startup(rdev);
if (r) {
/* Initialize surface registers */
radeon_surface_init(rdev);
/* Initialize surface registers */
radeon_surface_init(rdev);
+ radeon_pm_resume(rdev);
+
rdev->accel_working = true;
r = rs600_startup(rdev);
if (r) {
rdev->accel_working = true;
r = rs600_startup(rdev);
if (r) {
int rs600_suspend(struct radeon_device *rdev)
{
int rs600_suspend(struct radeon_device *rdev)
{
+ radeon_pm_suspend(rdev);
r600_audio_fini(rdev);
r100_cp_disable(rdev);
radeon_wb_disable(rdev);
r600_audio_fini(rdev);
r100_cp_disable(rdev);
radeon_wb_disable(rdev);
void rs600_fini(struct radeon_device *rdev)
{
void rs600_fini(struct radeon_device *rdev)
{
r600_audio_fini(rdev);
r100_cp_fini(rdev);
radeon_wb_fini(rdev);
r600_audio_fini(rdev);
r100_cp_fini(rdev);
radeon_wb_fini(rdev);
return r;
rs600_set_safe_registers(rdev);
return r;
rs600_set_safe_registers(rdev);
+ /* Initialize power management */
+ radeon_pm_init(rdev);
+
rdev->accel_working = true;
r = rs600_startup(rdev);
if (r) {
rdev->accel_working = true;
r = rs600_startup(rdev);
if (r) {
/* Initialize surface registers */
radeon_surface_init(rdev);
/* Initialize surface registers */
radeon_surface_init(rdev);
+ radeon_pm_resume(rdev);
+
rdev->accel_working = true;
r = rs690_startup(rdev);
if (r) {
rdev->accel_working = true;
r = rs690_startup(rdev);
if (r) {
int rs690_suspend(struct radeon_device *rdev)
{
int rs690_suspend(struct radeon_device *rdev)
{
+ radeon_pm_suspend(rdev);
r600_audio_fini(rdev);
r100_cp_disable(rdev);
radeon_wb_disable(rdev);
r600_audio_fini(rdev);
r100_cp_disable(rdev);
radeon_wb_disable(rdev);
void rs690_fini(struct radeon_device *rdev)
{
void rs690_fini(struct radeon_device *rdev)
{
r600_audio_fini(rdev);
r100_cp_fini(rdev);
radeon_wb_fini(rdev);
r600_audio_fini(rdev);
r100_cp_fini(rdev);
radeon_wb_fini(rdev);
return r;
rs600_set_safe_registers(rdev);
return r;
rs600_set_safe_registers(rdev);
+ /* Initialize power management */
+ radeon_pm_init(rdev);
+
rdev->accel_working = true;
r = rs690_startup(rdev);
if (r) {
rdev->accel_working = true;
r = rs690_startup(rdev);
if (r) {
/* Initialize surface registers */
radeon_surface_init(rdev);
/* Initialize surface registers */
radeon_surface_init(rdev);
+ radeon_pm_resume(rdev);
+
rdev->accel_working = true;
r = rv515_startup(rdev);
if (r) {
rdev->accel_working = true;
r = rv515_startup(rdev);
if (r) {
int rv515_suspend(struct radeon_device *rdev)
{
int rv515_suspend(struct radeon_device *rdev)
{
+ radeon_pm_suspend(rdev);
r100_cp_disable(rdev);
radeon_wb_disable(rdev);
rs600_irq_disable(rdev);
r100_cp_disable(rdev);
radeon_wb_disable(rdev);
rs600_irq_disable(rdev);
void rv515_fini(struct radeon_device *rdev)
{
void rv515_fini(struct radeon_device *rdev)
{
r100_cp_fini(rdev);
radeon_wb_fini(rdev);
radeon_ib_pool_fini(rdev);
r100_cp_fini(rdev);
radeon_wb_fini(rdev);
radeon_ib_pool_fini(rdev);
return r;
rv515_set_safe_registers(rdev);
return r;
rv515_set_safe_registers(rdev);
+ /* Initialize power management */
+ radeon_pm_init(rdev);
+
rdev->accel_working = true;
r = rv515_startup(rdev);
if (r) {
rdev->accel_working = true;
r = rv515_startup(rdev);
if (r) {
/* init golden registers */
rv770_init_golden_registers(rdev);
/* init golden registers */
rv770_init_golden_registers(rdev);
+ radeon_pm_resume(rdev);
+
rdev->accel_working = true;
r = rv770_startup(rdev);
if (r) {
rdev->accel_working = true;
r = rv770_startup(rdev);
if (r) {
int rv770_suspend(struct radeon_device *rdev)
{
int rv770_suspend(struct radeon_device *rdev)
{
+ radeon_pm_suspend(rdev);
r600_audio_fini(rdev);
uvd_v1_0_fini(rdev);
radeon_uvd_suspend(rdev);
r600_audio_fini(rdev);
uvd_v1_0_fini(rdev);
radeon_uvd_suspend(rdev);
+ /* Initialize power management */
+ radeon_pm_init(rdev);
+
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
void rv770_fini(struct radeon_device *rdev)
{
void rv770_fini(struct radeon_device *rdev)
{
r700_cp_fini(rdev);
r600_dma_fini(rdev);
r600_irq_fini(rdev);
r700_cp_fini(rdev);
r600_dma_fini(rdev);
r600_irq_fini(rdev);
-static int si_mc_load_microcode(struct radeon_device *rdev)
+int si_mc_load_microcode(struct radeon_device *rdev)
{
const __be32 *fw_data;
u32 running, blackout = 0;
{
const __be32 *fw_data;
u32 running, blackout = 0;
- r = si_mc_load_microcode(rdev);
- if (r) {
- DRM_ERROR("Failed to load MC firmware!\n");
- return r;
+ if (!rdev->pm.dpm_enabled) {
+ r = si_mc_load_microcode(rdev);
+ if (r) {
+ DRM_ERROR("Failed to load MC firmware!\n");
+ return r;
+ }
}
r = si_pcie_gart_enable(rdev);
}
r = si_pcie_gart_enable(rdev);
/* init golden registers */
si_init_golden_registers(rdev);
/* init golden registers */
si_init_golden_registers(rdev);
+ radeon_pm_resume(rdev);
+
rdev->accel_working = true;
r = si_startup(rdev);
if (r) {
rdev->accel_working = true;
r = si_startup(rdev);
if (r) {
int si_suspend(struct radeon_device *rdev)
{
int si_suspend(struct radeon_device *rdev)
{
+ radeon_pm_suspend(rdev);
dce6_audio_fini(rdev);
radeon_vm_manager_fini(rdev);
si_cp_enable(rdev, false);
dce6_audio_fini(rdev);
radeon_vm_manager_fini(rdev);
si_cp_enable(rdev, false);
+ /* Initialize power management */
+ radeon_pm_init(rdev);
+
ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
ring->ring_obj = NULL;
r600_ring_init(rdev, ring, 1024 * 1024);
ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
ring->ring_obj = NULL;
r600_ring_init(rdev, ring, 1024 * 1024);
void si_fini(struct radeon_device *rdev)
{
void si_fini(struct radeon_device *rdev)
{
si_cp_fini(rdev);
cayman_dma_fini(rdev);
si_fini_pg(rdev);
si_cp_fini(rdev);
cayman_dma_fini(rdev);
si_fini_pg(rdev);
struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
struct ni_ps *ni_get_ps(struct radeon_ps *rps);
struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
struct ni_ps *ni_get_ps(struct radeon_ps *rps);
+extern int si_mc_load_microcode(struct radeon_device *rdev);
+
static int si_populate_voltage_value(struct radeon_device *rdev,
const struct atom_voltage_table *table,
u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
static int si_populate_voltage_value(struct radeon_device *rdev,
const struct atom_voltage_table *table,
u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
void si_dpm_setup_asic(struct radeon_device *rdev)
{
void si_dpm_setup_asic(struct radeon_device *rdev)
{
+ int r;
+
+ r = si_mc_load_microcode(rdev);
+ if (r)
+ DRM_ERROR("Failed to load MC firmware!\n");
rv770_get_memory_type(rdev);
si_read_clock_registers(rdev);
si_enable_acpi_power_management(rdev);
rv770_get_memory_type(rdev);
si_read_clock_registers(rdev);
si_enable_acpi_power_management(rdev);