when xrun occurs, it will do snd_pcm_stop to disable spdif
and then clear logic, next snd_pcm_lib_write1 will trigger
snd_pcm_start to enable spdif, but not to excute hw_params
to configue spdif, so need to save spdif configuration to
reconfigure spdif.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
struct clk *clk;
struct device *dev;
struct snd_dmaengine_dai_dma_data dma_playback;
struct clk *clk;
struct device *dev;
struct snd_dmaengine_dai_dma_data dma_playback;
};
static inline struct rockchip_spdif_info *to_info(struct snd_soc_dai *cpu_dai)
};
static inline struct rockchip_spdif_info *to_info(struct snd_soc_dai *cpu_dai)
if (on) {
xfer |= XFER_TRAN_START;
dmacr |= DMACR_TRAN_DMA_ENABLE;
if (on) {
xfer |= XFER_TRAN_START;
dmacr |= DMACR_TRAN_DMA_ENABLE;
+ dmacr |= spdif->dmac;
+ writel(spdif->cfgr, regs + CFGR);
writel(dmacr, regs + DMACR);
writel(xfer, regs + XFER);
} else {
writel(dmacr, regs + DMACR);
writel(xfer, regs + XFER);
} else {
void __iomem *regs = spdif->regs;
unsigned long flags;
unsigned int val;
void __iomem *regs = spdif->regs;
unsigned long flags;
unsigned int val;
- int cfgr, dmac, intcr, chnregval;
+ u32 cfgr, dmac, intcr, chnregval;
char chnsta[CHNSTA_BYTES];
dev_dbg(spdif->dev, "%s\n", __func__);
char chnsta[CHNSTA_BYTES];
dev_dbg(spdif->dev, "%s\n", __func__);
cfgr &= ~CFGR_PRE_CHANGE_MASK;
cfgr |= CFGR_PRE_CHANGE_ENALBLE;
cfgr &= ~CFGR_PRE_CHANGE_MASK;
cfgr |= CFGR_PRE_CHANGE_ENALBLE;
writel(cfgr, regs + CFGR);
intcr = readl(regs + INTCR) & (~INTCR_SDBEIE_MASK);
writel(cfgr, regs + CFGR);
intcr = readl(regs + INTCR) & (~INTCR_SDBEIE_MASK);
dmac = readl(regs + DMACR) & (~DMACR_TRAN_DATA_LEVEL_MASK);
dmac |= DMA_DATA_LEVEL_16;
dmac = readl(regs + DMACR) & (~DMACR_TRAN_DATA_LEVEL_MASK);
dmac |= DMA_DATA_LEVEL_16;
writel(dmac, regs + DMACR);
/* channel status bit */
writel(dmac, regs + DMACR);
/* channel status bit */