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ARCv2: [axs103_smp] Reduce clk for Quad FPGA configs
authorVineet Gupta <vgupta@synopsys.com>
Mon, 3 Aug 2015 12:57:56 +0000 (18:27 +0530)
committerVineet Gupta <vgupta@synopsys.com>
Tue, 4 Aug 2015 03:56:30 +0000 (09:26 +0530)
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

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