+void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
+ const TargetInstrDesc &TID = MI.getDesc();
+
+ // Part of binary is determined by TableGn.
+ unsigned Binary = getBinaryCodeForInstr(MI);
+
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << ARMII::CondShift;
+
+ unsigned OpIdx = 0;
+
+ // Encode Dd / Sd.
+ unsigned RegD = getMachineOpValue(MI, OpIdx++);
+ Binary |= (RegD & 0x0f) << ARMII::RegRdShift;
+ Binary |= (RegD & 0x10) << ARMII::D_BitShift;
+
+ // Encode Dn / Sn.
+ if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPConv1Frm) {
+ unsigned RegN = getMachineOpValue(MI, OpIdx++);
+ Binary |= (RegN & 0x0f) << ARMII::RegRnShift;
+ Binary |= (RegN & 0x10) << ARMII::N_BitShift;
+
+ // FMRS / FMSR do not have Rm.
+ if (!TID.OpInfo[2].isPredicate()) {
+ unsigned RegM = getMachineOpValue(MI, OpIdx++);
+ Binary |= (RegM & 0x0f);
+ Binary |= (RegM & 0x10) << ARMII::M_BitShift;
+ }
+ } else {
+ unsigned RegM = getMachineOpValue(MI, OpIdx++);
+ Binary |= (RegM & 0x0f);
+ Binary |= (RegM & 0x10) << ARMII::M_BitShift;
+ }
+
+ emitWordLE(Binary);
+}
+