-+ }
-+ break;
-+ case BCMA_CHIP_ID_BCM53018:
-+ /* USB3 PLL Block */
-+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
-+ iowrite32(0x587e8000, ccb->mii + 0x004);
-+
-+ /* Assert Ana_Pllseq start */
-+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
-+ iowrite32(0x58061000, ccb->mii + 0x004);
-+
-+ /* Assert CML Divider ratio to 26 */
-+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
-+ iowrite32(0x582a6400, ccb->mii + 0x004);
-+
-+ /* Asserting PLL Reset */
-+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
-+ iowrite32(0x582ec000, ccb->mii + 0x004);
-+
-+ /* Deaaserting PLL Reset */
-+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
-+ iowrite32(0x582e8000, ccb->mii + 0x004);
-+
-+ /* Waiting MII Mgt interface idle */
-+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
-+
-+ /* Deasserting USB3 system reset */
-+ bcma_awrite32(core, BCMA_RESET_CTL, 0);
-+
-+ /* PLL frequency monitor enable */
-+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
-+ iowrite32(0x58069000, ccb->mii + 0x004);
-+
-+ /* PIPE Block */
-+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
-+ iowrite32(0x587e8060, ccb->mii + 0x004);
-+
-+ /* CMPMAX & CMPMINTH setting */
-+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
-+ iowrite32(0x580af30d, ccb->mii + 0x004);
-+
-+ /* DEGLITCH MIN & MAX setting */
-+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
-+ iowrite32(0x580e6302, ccb->mii + 0x004);
-+
-+ /* TXPMD block */
-+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
-+ iowrite32(0x587e8040, ccb->mii + 0x004);
-+
-+ /* Enabling SSC */
-+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
-+ iowrite32(0x58061003, ccb->mii + 0x004);
-+
-+ /* Waiting MII Mgt interface idle */
-+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
-+
-+ break;